Lines Matching refs:counter
4 * ARM performance counter support.
45 * cycle counter CCNT + 31 events counters CNT0..30.
59 * A 1 bit for an index indicates that the counter is being used for
60 * an event. A 0 means that the counter can be used.
65 * A 1 bit for an index indicates that the counter is actively being
263 * were throttled we simply disabled the IRQ source and the counter
280 /* If we don't have a space for the counter then finish early. */
288 * If there is an event in the counter we are going to use then make
449 * Check whether we need to exclude the counter from certain modes.
471 * the event mapping and the counter to use. The counter to use is
560 * ARMv6 Performance counter handling code.
562 * ARMv6 has 2 configurable performance counters and a single cycle counter.
571 * the event bus. The procedure for disabling a configurable counter is:
572 * - change the counter to count the ETMEXTOUT[0] signal (0x20). This
573 * effectively stops the counter from counting.
574 * - disable the counter's interrupt generation (each counter has it's
576 * Once stopped, the counter value can be written as 0 to reset.
578 * To enable a counter:
579 * - enable the counter's interrupt generation.
582 * Note: the dedicated cycle counter only counts cycles and can't be
584 * cycle counter, we have to just disable the interrupt reporting and start
585 * ignoring that counter. When re-enabling, we have to reset the value and
688 * want the main TLB misses they can use a raw counter.
825 * want the main TLB misses they can use a raw counter.
911 enum armv6_counters counter)
915 if (ARMV6_CYCLE_COUNTER == counter)
917 else if (ARMV6_COUNTER0 == counter)
919 else if (ARMV6_COUNTER1 == counter)
922 WARN_ONCE(1, "invalid counter number (%d)\n", counter);
928 armv6pmu_read_counter(int counter)
932 if (ARMV6_CYCLE_COUNTER == counter)
934 else if (ARMV6_COUNTER0 == counter)
936 else if (ARMV6_COUNTER1 == counter)
939 WARN_ONCE(1, "invalid counter number (%d)\n", counter);
945 armv6pmu_write_counter(int counter,
948 if (ARMV6_CYCLE_COUNTER == counter)
950 else if (ARMV6_COUNTER0 == counter)
952 else if (ARMV6_COUNTER1 == counter)
955 WARN_ONCE(1, "invalid counter number (%d)\n", counter);
976 WARN_ONCE(1, "invalid counter number (%d)\n", idx);
981 * Mask out the current event and set the counter to count the event
1026 * each counter has overflowed before we process it.
1105 /* Always place a cycle counter into the cycle counter. */
1113 * For anything other than a cycle counter, try and use
1145 WARN_ONCE(1, "invalid counter number (%d)\n", idx);
1150 * Mask out the current event and set the counter to count the number
1175 WARN_ONCE(1, "invalid counter number (%d)\n", idx);
1237 * a single cycle counter.
1239 * a single cycle counter.
1242 * counter and all 4 performance counters together can be reset separately.
1437 * If users want the DTLB refills misses a raw counter
1553 * If users want the DTLB refills misses a raw counter
1605 ARMV7_CYCLE_COUNTER = 1, /* Cycle counter */
1606 ARMV7_COUNTER0 = 2, /* First event counter */
1610 * The cycle counter is ARMV7_CYCLE_COUNTER.
1611 * The first event counter is ARMV7_COUNTER0.
1612 * The last event counter is (ARMV7_COUNTER0 + armpmu->num_events - 1).
1625 #define ARMV7_PMNC_C (1 << 2) /* Cycle counter reset */
1636 #define ARMV7_CNT0 0 /* First event counter */
1637 #define ARMV7_CCNT 31 /* Cycle counter */
1703 enum armv7_counters counter)
1707 if (counter == ARMV7_CYCLE_COUNTER)
1709 else if ((counter >= ARMV7_COUNTER0) && (counter <= ARMV7_COUNTER_LAST))
1710 ret = pmnc & ARMV7_FLAG_P(counter);
1712 pr_err("CPU%u checking wrong counter %d overflow status\n",
1713 smp_processor_id(), counter);
1723 pr_err("CPU%u selecting wrong PMNC counter"
1745 pr_err("CPU%u reading wrong counter %d\n",
1760 pr_err("CPU%u writing wrong counter %d\n",
1778 pr_err("CPU%u enabling wrong PMNC counter"
1800 pr_err("CPU%u disabling wrong PMNC counter"
1821 pr_err("CPU%u enabling wrong PMNC counter"
1842 pr_err("CPU%u disabling wrong PMNC counter"
1914 * Enable counter and interrupt, and set the counter to count
1920 * Disable counter
1932 * Enable interrupt for this counter
1937 * Enable counter
1949 * Disable counter and interrupt
1954 * Disable counter
1959 * Disable interrupt for this counter
1986 * Handle the counter(s) overflow(s)
2002 * each counter has overflowed before we process it.
2075 /* Always place a cycle counter into the cycle counter. */
2083 * For anything other than a cycle counter, try and use
2119 /* Add the CPU cycles counter and return */
2124 * ARMv5 [xscale] Performance counter handling code.
2129 * - xscale1pmu: 2 event counters and a cycle counter
2130 * - xscale2pmu: 4 event counters and a cycle counter
2319 enum xscale_counters counter)
2323 switch (counter) {
2334 WARN_ONCE(1, "invalid counter number (%d)\n", counter);
2418 WARN_ONCE(1, "invalid counter number (%d)\n", idx);
2449 WARN_ONCE(1, "invalid counter number (%d)\n", idx);
2508 xscale1pmu_read_counter(int counter)
2512 switch (counter) {
2528 xscale1pmu_write_counter(int counter, u32 val)
2530 switch (counter) {
2640 enum xscale_counters counter)
2644 switch (counter) {
2661 WARN_ONCE(1, "invalid counter number (%d)\n", counter);
2757 WARN_ONCE(1, "invalid counter number (%d)\n", idx);
2800 WARN_ONCE(1, "invalid counter number (%d)\n", idx);
2851 xscale2pmu_read_counter(int counter)
2855 switch (counter) {
2877 xscale2pmu_write_counter(int counter, u32 val)
2879 switch (counter) {