Lines Matching defs:uengine
21 #include <asm/hardware/uengine.h>
58 static void *ixp2000_uengine_csr_area(int uengine)
60 return ((void *)IXP_UENGINE_CSR_VIRT_BASE) + (uengine << 10);
71 u32 ixp2000_uengine_csr_read(int uengine, int offset)
78 uebase = ixp2000_uengine_csr_area(uengine);
90 void ixp2000_uengine_csr_write(int uengine, int offset, u32 value)
96 uebase = ixp2000_uengine_csr_area(uengine);
118 void ixp2000_uengine_set_mode(int uengine, u32 mode)
125 ixp2000_uengine_csr_write(uengine, CTX_ENABLES, mode);
130 ixp2000_uengine_csr_write(uengine, CC_ENABLE, 0x00002000);
135 ixp2000_uengine_csr_write(uengine, NN_PUT, 0x00);
136 ixp2000_uengine_csr_write(uengine, NN_GET, 0x00);
137 ixp2000_uengine_csr_write(uengine, T_INDEX_BYTE_INDEX, 0);
146 static void ustore_write(int uengine, u64 insn)
158 ixp2000_uengine_csr_write(uengine, USTORE_DATA_LOWER, (u32)insn);
159 ixp2000_uengine_csr_write(uengine, USTORE_DATA_UPPER, (u32)(insn >> 32));
162 void ixp2000_uengine_load_microcode(int uengine, u8 *ucode, int insns)
169 ixp2000_uengine_csr_write(uengine, USTORE_ADDRESS, 0x80000000);
180 ustore_write(uengine, insn);
192 addr = ixp2000_uengine_csr_read(uengine, USTORE_ADDRESS);
195 ustore_write(uengine, 0xf0000c0300ULL);
201 ixp2000_uengine_csr_write(uengine, USTORE_ADDRESS, 0x00000000);
205 void ixp2000_uengine_init_context(int uengine, int context, int pc)
210 ixp2000_uengine_csr_write(uengine, CSR_CTX_POINTER, context);
215 ixp2000_uengine_csr_write(uengine, INDIRECT_CTX_SIG_EVENTS, 1);
216 ixp2000_uengine_csr_write(uengine, INDIRECT_CTX_WAKEUP_EVENTS, 1);
221 ixp2000_uengine_csr_write(uengine, INDIRECT_CTX_STS, pc);
225 void ixp2000_uengine_start_contexts(int uengine, u8 ctx_mask)
232 mask = ixp2000_uengine_csr_read(uengine, CTX_ENABLES);
234 ixp2000_uengine_csr_write(uengine, CTX_ENABLES, mask);
238 void ixp2000_uengine_stop_contexts(int uengine, u8 ctx_mask)
246 mask = ixp2000_uengine_csr_read(uengine, CTX_ENABLES);
248 ixp2000_uengine_csr_write(uengine, CTX_ENABLES, mask);
368 static int set_initial_registers(int uengine, struct ixp2000_uengine_code *c)
410 ixp2000_uengine_load_microcode(uengine, ucode, 513);
411 ixp2000_uengine_init_context(uengine, 0, 0);
412 ixp2000_uengine_start_contexts(uengine, 0x01);
416 status = ixp2000_uengine_csr_read(uengine, ACTIVE_CTX_STS);
420 ixp2000_uengine_stop_contexts(uengine, 0x01);
429 int ixp2000_uengine_load(int uengine, struct ixp2000_uengine_code *c)
436 if (!(ixp2000_uengine_mask & (1 << uengine)))
439 ixp2000_uengine_reset(1 << uengine);
440 ixp2000_uengine_set_mode(uengine, c->uengine_parameters);
441 if (set_initial_registers(uengine, c))
443 ixp2000_uengine_load_microcode(uengine, c->insns, c->num_insns);
446 ixp2000_uengine_init_context(uengine, ctx, 0);
455 int uengine;
496 for (uengine = 0; uengine < 32; uengine++) {
497 if (ixp2000_uengine_mask & (1 << uengine)) {
498 ixp2000_uengine_csr_write(uengine, TIMESTAMP_LOW, 0);
499 ixp2000_uengine_csr_write(uengine, TIMESTAMP_HIGH, 0);