Lines Matching defs:csrs
172 io7_ioport_csrs *csrs;
180 csrs = IO7_CSRS_KERN(io7->pe, port);
182 csrs->POx_ERR_SUM.csr = -1UL;
183 csrs->POx_TLB_ERR.csr = -1UL;
184 csrs->POx_SPL_COMPLT.csr = -1UL;
185 csrs->POx_TRANS_SUM.csr = -1UL;
210 io7_ioport_csrs *csrs = IO7_CSRS_KERN(io7->pe, port);
226 io7_port->csrs = csrs;
267 io7_port->saved_wbase[i] = csrs->POx_WBASE[i].csr;
268 io7_port->saved_wmask[i] = csrs->POx_WMASK[i].csr;
269 io7_port->saved_tbase[i] = csrs->POx_TBASE[i].csr;
292 csrs->POx_WBASE[0].csr =
294 csrs->POx_WMASK[0].csr = (hose->sg_isa->size - 1) & wbase_m_addr;
295 csrs->POx_TBASE[0].csr = virt_to_phys(hose->sg_isa->ptes);
300 csrs->POx_WBASE[1].csr = __direct_map_base | wbase_m_ena;
301 csrs->POx_WMASK[1].csr = (__direct_map_size - 1) & wbase_m_addr;
302 csrs->POx_TBASE[1].csr = 0;
310 csrs->POx_WBASE[2].csr =
312 csrs->POx_WMASK[2].csr = (hose->sg_pci->size - 1) & wbase_m_addr;
313 csrs->POx_TBASE[2].csr = virt_to_phys(hose->sg_pci->ptes);
318 csrs->POx_WBASE[3].csr = 0;
323 csrs->POx_CTRL.csr &= ~(1UL << 61);
326 csrs->POx_MSK_HEI.csr &= ~(3UL << 14);
343 io7->csrs = IO7_PORT7_CSRS_KERN(io7->pe);
349 io7_ioport_csrs *csrs = IO7_CSRS_KERN(io7->pe, i);
350 if (csrs->POx_CACHE_CTL.csr == 8) {
603 io7_ioport_csrs *csrs = ((struct io7_port *)hose->sysdata)->csrs;
606 csrs->POx_SG_TBIA.csr = 0;
608 csrs->POx_SG_TBIA.csr;
952 io7_ioport_csrs *csrs = ((struct io7_port *)agp->hose->sysdata)->csrs;
962 agp_pll = io7->csrs->POx_RST[IO7_AGP_PORT].csr;
1008 csrs->AGP_CMD.csr = agp->mode.lw;
1064 io7_ioport_csrs *csrs;
1091 * Get the csrs from the hose.
1093 csrs = ((struct io7_port *)hose->sysdata)->csrs;
1123 agp->capability.lw = csrs->AGP_STAT.csr;
1129 agp->mode.lw = csrs->AGP_CMD.csr;