Lines Matching refs:loop
15 # - modulo-scheduling outer loop would eliminate quite a number of
16 # stalls after ldf8, xma and getf.sig outside inner loop and
34 # core loop happens to match 512-bit timing. Either way, it resulted
146 brp.loop.imp .L1st_ctop,.L1st_cend-16
213 brp.loop.imp .Linner_ctop,.Linner_cend-16
235 // This loop spins in 4*(n+7) ticks on Itanium 2 and should spin in
304 brp.loop.imp .Lsub_ctop,.Lsub_cend-16
333 brp.loop.imp .Lcopy_ctop,.Lcopy_cend-16
372 .skip 48 // aligns loop body
487 brp.loop.imp .Louter_8_ctop,.Louter_8_cend-16
491 // The loop is scheduled for 32*n ticks on Itanium 2. Actual attempt
662 // above loop has to execute one more time, without (p16), which is
760 // carrybit|tmp[8] layout upon exit from above loop is: