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  • only in /netgear-R7000-V1.0.7.12_1.2.5/ap/gpl/minidlna/ffmpeg-2.3.4/libavcodec/ppc/

Lines Matching defs:s3

33 #define STEP8(s0, s1, s2, s3, s4, s5, s6, s7, vec_rnd) \
50 t0 = vec_sl(vec_add(s1, s3), vec_4); \
53 t0 = vec_add(t0, vec_sub(s5, s3)); \
57 t1 = vec_sub(t1, vec_sl(s3, vec_2)); \
60 t2 = vec_sl(vec_sub(s7, s3), vec_4); \
66 t3 = vec_sub(t3, vec_sl(s3, vec_3)); \
68 t3 = vec_sub(t3, vec_add(s3, s5)); \
73 s3 = vec_add(t7, t3); \
80 #define SHIFT_HOR8(s0, s1, s2, s3, s4, s5, s6, s7) \
85 s3 = vec_sra(s3, vec_3); \
92 #define SHIFT_VERT8(s0, s1, s2, s3, s4, s5, s6, s7) \
97 s3 = vec_sra(s3, vec_7); \
105 #define STEP4(s0, s1, s2, s3, vec_rnd) \
112 t3 = vec_sl(vec_sub(s3, s1), vec_1); \
115 t3 = vec_add(t3, vec_sl(s3, vec_3)); \
116 t3 = vec_add(t3, vec_sl(s3, vec_2)); \
120 s3 = vec_sub(t0, t2); \
123 #define SHIFT_HOR4(s0, s1, s2, s3) \
127 s3 = vec_sra(s3, vec_3);
129 #define SHIFT_VERT4(s0, s1, s2, s3) \
133 s3 = vec_sra(s3, vec_7);
140 vector signed int s0, s1, s2, s3, s4, s5, s6, s7;
164 s3 = vec_unpackl(src3);
177 STEP8(s0, s1, s2, s3, s4, s5, s6, s7, vec_4s);
178 SHIFT_HOR8(s0, s1, s2, s3, s4, s5, s6, s7);
184 src3 = vec_pack(sB, s3);
194 s3 = vec_unpackl(src3);
207 STEP8(s0, s1, s2, s3, s4, s5, s6, s7, vec_64);
208 SHIFT_VERT8(s0, s1, s2, s3, s4, s5, s6, s7);
214 src3 = vec_pack(sB, s3);
235 vector signed int s0, s1, s2, s3, s4, s5, s6, s7;
263 s3 = vec_unpackl(src3);
276 STEP8(s0, s1, s2, s3, s4, s5, s6, s7, vec_4s);
277 SHIFT_HOR8(s0, s1, s2, s3, s4, s5, s6, s7);
283 src3 = vec_pack(sB, s3);
293 s3 = vec_unpackh(src3);
298 STEP4(s0, s1, s2, s3, vec_64);
299 SHIFT_VERT4(s0, s1, s2, s3);
305 src3 = vec_pack(s3, sB);