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  • only in /netgear-R7000-V1.0.7.12_1.2.5/ap/gpl/minidlna/ffmpeg-2.3.4/libavcodec/arm/

Lines Matching refs:t4

100         vmul.i16        q11, q3,  d0[1]             @ t4 = 22 * (src[3])
106 vmls.i16 q11, q1, d1[0] @ t4 -= 10 * src[1]
110 vhsub.s16 q1, q9, q11 @ dst[1] = (t2 - t4) >> 1
111 vhadd.s16 q2, q9, q11 @ dst[2] = (t2 + t4) >> 1
144 vshl.i16 q15, q2, #4 @ t3|t4 = 16 * (src[16]|src[48])
150 vneg.s16 d31, d31 @ t4 = -t4
151 vmla.i16 q15, q2, d0[1] @ t3|t4 += 6 * (src[48]|src[16])
159 @ q15 old t3|t4
168 vsub.i16 q9, q13, q12 @ t3|t4 = - (temp3a|temp4a) + (temp3b|temp4b)
175 vsub.i16 q11, q14, q15 @ t8|t7 = old t1|t2 - old t3|t4
176 vadd.i16 q10, q14, q15 @ t5|t6 = old t1|t2 + old t3|t4
182 vsub.i16 d19, d19, d25 @ t4 -= temp4
187 vmla.i16 q9, q1, d0[2] @ t3|t4 += 15 * src[56]|src[40]
194 @ t4 d19
208 vhadd.s16 q1, q9, q11 @ line[2,3] = (t3|t4 + t7|t8) >> 1
211 vhsub.s16 q2, q2, q9 @ line[5,4] = (t7|t8 - t3|t4 + 1) >> 1
214 vhsub.s16 q2, q11, q9 @ line[5,4] = (t7|t8 - t3|t4) >> 1
239 @ This actually computes half of t1, t2, t3, t4, as explained below
244 vmul.i16 q2, q10, q0 @ t4 = 6/2 * src[16]
254 vsub.i16 q2, q2, q3 @ t4 = 6/2 * src[16] - 16/2 * src[48]
265 @ q2 old t4
280 vshl.i16 q10, q9, #2 @ t4 = 4 * src[8]
286 vmls.i16 q10, q11, d0[1] @ t4 -= 9 * src[24]
291 vmla.i16 q10, q13, d0[0] @ t4 += 15 * src[40]
296 @ Compute t5, t6, t7, t8 from old t1, t2, t3, t4. Actually, it computes
297 @ half of t5, t6, t7, t8 since t1, t2, t3, t4 are halved.
300 vadd.i16 q13, q12, q2 @ t6 = t2 + t4
301 vsub.i16 q2, q12, q2 @ t7 = t2 - t4
312 vmls.i16 q10, q15, d1[0] @ t4 -= 16 * src[56]
319 @ t4 q10
370 vadd.i16 q11, q1, q10 @ q11 = t8half + t4
372 vsub.i16 q10, q10, q12 @ q10 = t4 - 1
381 vsub.i16 q10, q1, q10 @ q10 = t8half - t4 + 1
382 vhadd.s16 q11, q1, q11 @ q11 = (t8half + t8half + t4) >> 1
385 vhadd.s16 q12, q1, q10 @ q12 = (t8half + t8half - t4 + 1) >> 1
585 vmul.i16 q3, q14, q1 @ t3|t4 = 22 * (src[1]|src[3])
588 vmls.i16 d7, d30, d2 @ t4 -= 10 * src[1]
590 vadd.i16 q0, q2, q3 @ dst[0,2] = (t1|t2 + t3|t4)
591 vsub.i16 q1, q2, q3 @ dst[3,1] = (t1|t2 - t3|t4)
614 vc1_inv_trans_4x4_helper add=4 rshift=3 @ compute t1, t2, t3, t4 and combine them into dst[0-3]
638 vc1_inv_trans_4x4_helper add=64 rshift=7 @ compute t1, t2, t3, t4 and combine them into dst[0-3]