dist/ar5312/ar5312_reset.c

23 #include "ah.h"
39 extern HAL_BOOL ar5212SetTransmitPower(struct ath_hal *ah,
50 write_common(struct ath_hal *ah, const HAL_INI_ARRAY *ia,
65 			OS_REG_WRITE(ah, reg, V(i, 1));
83 ar5312Reset(struct ath_hal *ah, HAL_OPMODE opmode,
88 	struct ath_hal_5212 *ahp = AH5212(ah);
101 	HALASSERT(ah->ah_magic == AR5212_MAGIC);
102 	ee = AH_PRIVATE(ah)->ah_eeprom;
104 	OS_MARK(ah, AH_MARK_RESET, bChannelChange);
107 		HALDEBUG(ah, HAL_DEBUG_ANY,
113 		HALDEBUG(ah, HAL_DEBUG_ANY,
122 	ichan = ath_hal_checkchannel(ah, chan);
124 		HALDEBUG(ah, HAL_DEBUG_ANY,
136 		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid operating mode %u\n",
165 		saveFrameSeqCount = OS_REG_READ(ah, AR_D_SEQNUM);
170 	if ((IS_2413(ah) || IS_5413(ah))) {
179 		    (AH_PRIVATE(ah)->ah_curchan != AH_NULL) &&
180 		    (chan->channel != AH_PRIVATE(ah)->ah_curchan->channel) &&
182 		     (AH_PRIVATE(ah)->ah_curchan->channelFlags & CHANNEL_ALL))) {
183 			if (ar5212ChannelChange(ah, chan))
192 	saveDefAntenna = OS_REG_READ(ah, AR_DEF_ANTENNA);
197 	macStaId1 = OS_REG_READ(ah, AR_STA_ID1) &
201 	if (!IS_5315(ah))
202 		saveLedState = OS_REG_READ(ah, AR5312_PCICFG) &
206 	ar5312RestoreClock(ah, opmode);		/* move to refclk operation */
212 	(void) ar5212GetRfgain(ah);
214 	if (!ar5312ChipReset(ah, chan)) {
215 		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__);
242 		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n",
247 	OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__);
250 	OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
252 	regWrites = ath_hal_ini_write(ah, &ahp->ah_ini_modes, modesIndex, 0);
253 	regWrites = write_common(ah, &ahp->ah_ini_common, bChannelChange,
255 	ahp->ah_rfHal->writeRegs(ah, modesIndex, freqIndex, regWrites);
257 	OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__);
260 		ar5212SetIFSTiming(ah, chan);
264 	if (AH_PRIVATE(ah)->ah_phyRev >= AR_PHY_CHIP_ID_REV_2) {
266 		OS_REG_WRITE(ah, AR_PHY_ADC_CTL,
280 			OS_REG_WRITE(ah, AR_PHY_TXPWRADJ,
284 			OS_REG_WRITE(ah, AR_PHY_TXPWRADJ, 0);
288 		OS_REG_CLR_BIT(ah, AR_PHY_DAG_CTRLCCK,
290 		OS_REG_RMW_FIELD(ah, AR_PHY_DAG_CTRLCCK,
294 		OS_REG_WRITE(ah, AR_SEQ_MASK, 0x0000000F);
297 	if (AH_PRIVATE(ah)->ah_phyRev >= AR_PHY_CHIP_ID_REV_3) {
299 		OS_REG_WRITE(ah, AR_PHY_BLUETOOTH,  0);
301 	if (AH_PRIVATE(ah)->ah_phyRev >= AR_PHY_CHIP_ID_REV_4) {
304 		OS_REG_RMW_FIELD(ah, AR_D_FPCTL, ... );
306 		OS_REG_CLR_BIT(ah, AR_TXCFG, AR_TXCFG_DBL_BUF_DIS);
310 	if (IS_5312_2_X(ah)) {
312 		OS_REG_WRITE(ah, AR_PHY_SIGMA_DELTA,
319 			OS_REG_RMW_FIELD(ah, AR_PHY_RXGAIN, AR_PHY_RXGAIN_TXRX_RF_MAX, 0x0F);
323 			OS_REG_RMW_FIELD(ah, AR_PHY_CCK_RXCTRL4, AR_PHY_CCK_RXCTRL4_FREQ_EST_SHORT, 12);
326 		OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x04);
330 			OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_AGC, 32);
333 		OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x0e);
337 	if (!ar5212SetTransmitPower(ah, ichan, rfXpdGain)) {
338 		HALDEBUG(ah, HAL_DEBUG_ANY,
344 	if (!ahp->ah_rfHal->setRfRegs(ah, ichan, modesIndex, rfXpdGain)) {
345 		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: ar5212SetRfRegs failed\n",
352 		if ((IS_5413(ah) || (AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER5_3)) &&
354 			ar5212SetSpurMitigation(ah, ichan);
355 		ar5212SetDeltaSlope(ah, chan);
359 	if (!ar5212SetBoardValues(ah, ichan)) {
360 		HALDEBUG(ah, HAL_DEBUG_ANY,
367 		OS_REG_WRITE(ah, AR_D_SEQNUM, saveFrameSeqCount);
369 	OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__);
371 	OS_REG_WRITE(ah, AR_STA_ID0, LE_READ_4(ahp->ah_macaddr));
372 	OS_REG_WRITE(ah, AR_STA_ID1, LE_READ_2(ahp->ah_macaddr + 4)
377 	ar5212SetOperatingMode(ah, opmode);
380 	OS_REG_WRITE(ah, AR_BSSMSKL, LE_READ_4(ahp->ah_bssidmask));
381 	OS_REG_WRITE(ah, AR_BSSMSKU, LE_READ_2(ahp->ah_bssidmask + 4));
384 	if (!IS_5315(ah))
385 		OS_REG_WRITE(ah, AR5312_PCICFG, OS_REG_READ(ah, AR_PCICFG) | saveLedState);
388 	OS_REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
391 	OS_REG_WRITE(ah, AR_BSS_ID0, LE_READ_4(ahp->ah_bssid));
392 	OS_REG_WRITE(ah, AR_BSS_ID1, LE_READ_2(ahp->ah_bssid + 4));
395 	OS_REG_WRITE(ah, AR_RSSI_THR, ahp->ah_rssiThr);
397 	OS_REG_WRITE(ah, AR_ISR, ~0);		/* cleared on write */
399 	if (!ar5212SetChannel(ah, ichan))
402 	OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__);
404 	ar5212SetCoverageClass(ah, AH_PRIVATE(ah)->ah_coverageClass, 1);
406 	ar5212SetRateDurationTable(ah, chan);
409 	if (IS_RAD5112_ANY(ah) &&
410 	    (IS_CHAN_HALF_RATE(AH_PRIVATE(ah)->ah_curchan) ||
411 	     IS_CHAN_QUARTER_RATE(AH_PRIVATE(ah)->ah_curchan))) {
413 			(IS_CHAN_HALF_RATE(AH_PRIVATE(ah)->ah_curchan)) ?
416 		OS_REG_RMW_FIELD(ah, AR_PHY_TX_CTL,
438 	if (IS_5312_2_X(ah)) {
439 		(void) OS_REG_READ(ah, AR_PHY_SLEEP_SCAL);
447 	synthDelay = OS_REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
455 	OS_REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
464 	if (IS_CHAN_HALF_RATE(AH_PRIVATE(ah)->ah_curchan)) {
466 	} else if (IS_CHAN_QUARTER_RATE(AH_PRIVATE(ah)->ah_curchan)) {
476 	testReg = OS_REG_READ(ah, AR_PHY_TESTCTRL);
478 	OS_REG_WRITE(ah, AR_PHY_TESTCTRL, AR_PHY_TESTCTRL_TXHOLD);
481 	       (OS_REG_READ(ah, 0x9c24) & 0x10)) /* test if baseband not ready */		OS_DELAY(200);
482 	OS_REG_WRITE(ah, AR_PHY_TESTCTRL, testReg);
485 	OS_REG_WRITE(ah, AR_PHY_AGC_CONTROL,
486 		  OS_REG_READ(ah, AR_PHY_AGC_CONTROL)
492 		OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4,
495 		OS_REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4,
502 	ar5212SetCompRegs(ah);
506 		OS_REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
509 	for (i = 0; i < AH_PRIVATE(ah)->ah_caps.halTotalQueues; i++)
510 		ar5212ResetTxQueue(ah, i);
524 	OS_REG_WRITE(ah, AR_IMR, ahp->ah_maskReg);
526 	OS_REG_WRITE(ah, AR_IMR_S2,
527 		OS_REG_READ(ah, AR_IMR_S2)
530 	if (AH_PRIVATE(ah)->ah_rfkillEnabled)
531 		ar5212EnableRfKill(ah);
533 	if (!ath_hal_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, 0)) {
534 		HALDEBUG(ah, HAL_DEBUG_ANY,
543 	ar5312SetupClock(ah, opmode);
551 	OS_REG_WRITE(ah, AR_BEACON,
552 		(OS_REG_READ(ah, AR_BEACON) &~ (AR_BEACON_EN | AR_BEACON_RESET_TSF)));
557 	if (AH_PRIVATE(ah)->ah_macVersion > AR_SREV_VERSION_VENICE ||
558 	    (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE &&
559 	     AH_PRIVATE(ah)->ah_macRev >= AR_SREV_GRIFFIN_LITE)) {
560 		OS_REG_WRITE(ah, AR_QOS_CONTROL, 0x100aa);	/* XXX magic */
561 		OS_REG_WRITE(ah, AR_QOS_SELECT, 0x3210);	/* XXX magic */
565 	OS_REG_WRITE(ah, AR_NOACK,
572 		OS_REG_WRITE(ah, AR_MISC_MODE, ahp->ah_miscMode);
574 		ar5212SetSlotTime(ah, ahp->ah_slottime);
576 		ar5212SetAckTimeout(ah, ahp->ah_acktimeout);
578 		ar5212SetCTSTimeout(ah, ahp->ah_ctstimeout);
580 		ar5212SetSifsTime(ah, ahp->ah_sifstime);
581 	if (AH_PRIVATE(ah)->ah_diagreg != 0)
582 		OS_REG_WRITE(ah, AR_DIAG_SW, AH_PRIVATE(ah)->ah_diagreg);
584 	AH_PRIVATE(ah)->ah_opmode = opmode;	/* record operating mode */
593 	HALDEBUG(ah, HAL_DEBUG_RESET, "%s: done\n", __func__);
595 	OS_MARK(ah, AH_MARK_RESET_DONE, 0);
599 	OS_MARK(ah, AH_MARK_RESET_DONE, ecode);
614 ar5312PhyDisable(struct ath_hal *ah)
616     return ar5312SetResetReg(ah, AR_RC_BB);
623 ar5312Disable(struct ath_hal *ah)
625 	if (!ar5312SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE))
631 	return ar5312SetResetReg(ah, AR_RC_MAC | AR_RC_BB);
642 ar5312ChipReset(struct ath_hal *ah, HAL_CHANNEL *chan)
645 	OS_MARK(ah, AH_MARK_CHIPRESET, chan ? chan->channel : 0);
650 	if (!ar5312SetResetReg(ah, AR_RC_MAC | AR_RC_BB)) {
651 		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: ar5312SetResetReg failed\n",
657 	if (!ar5312SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) {
658 		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: ar5312SetPowerMode failed\n",
664 	if (!ar5312SetResetReg(ah, 0)) {
665 		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: ar5312SetResetReg failed\n",
683 		if (IS_RAD5112_ANY(ah)) {
685 			if (!IS_5315(ah)) {
731 		curPhyPLL = OS_REG_READ(ah, AR_PHY_PLL_CTL);
740 			OS_REG_WRITE(ah, AR_PHY_TURBO, turbo);
741 			OS_REG_WRITE(ah, AR_PHY_MODE, rfMode);
743 				OS_REG_WRITE(ah,  AR_PHY_PLL_CTL,  phyPLL);
749 				OS_REG_WRITE(ah,  AR_PHY_PLL_CTL,  phyPLL);
753 			OS_REG_WRITE(ah, AR_PHY_TURBO, turbo);
754 			OS_REG_WRITE(ah, AR_PHY_MODE, rfMode);
764 ar5312SetResetReg(struct ath_hal *ah, uint32_t resetMask)
769         if ((rt = ar5312MacReset(ah, mask)) == AH_FALSE) {
784 			OS_REG_WRITE(ah, AR_CFG, mask);
786 			OS_REG_WRITE(ah, AR_CFG, INIT_CONFIG_STATUS);
798 ar5312MacReset(struct ath_hal *ah, unsigned int RCMask)
800 	int wlanNum = AR5312_UNIT(ah);
807 	    if (IS_5315(ah)) {
825 			reg = OS_REG_READ(ah,
826 							  (AR5315_RSTIMER_BASE - ((uint32_t) ah->ah_sh) + AR5315_RESET));
839 			OS_REG_WRITE(ah,
840 						 (AR5315_RSTIMER_BASE - ((uint32_t) ah->ah_sh)+AR5315_RESET),
843 			OS_REG_READ(ah,
844 						(AR5315_RSTIMER_BASE - ((uint32_t) ah->ah_sh) +AR5315_RESET));
850 			OS_REG_READ(ah,
851 						(AR5315_RSTIMER_BASE- ((uint32_t) ah->ah_sh) +AR5315_RESET));
852 			OS_REG_WRITE(ah,
853 						 (AR5315_RSTIMER_BASE - ((uint32_t) ah->ah_sh)+AR5315_RESET),
856 			OS_REG_READ(ah,
857 						(AR5315_RSTIMER_BASE- ((uint32_t) ah->ah_sh) +AR5315_RESET));
882 			reg = OS_REG_READ(ah,
883 							  (AR5312_RSTIMER_BASE - ((uint32_t) ah->ah_sh) + AR5312_RESET));
896 			OS_REG_WRITE(ah,
897 						 (AR5312_RSTIMER_BASE - ((uint32_t) ah->ah_sh)+AR5312_RESET),
900 			OS_REG_READ(ah,
901 						(AR5312_RSTIMER_BASE - ((uint32_t) ah->ah_sh) +AR5312_RESET));
907 			OS_REG_READ(ah,
908 						(AR5312_RSTIMER_BASE- ((uint32_t) ah->ah_sh) +AR5312_RESET));
909 			OS_REG_WRITE(ah,
910 						 (AR5312_RSTIMER_BASE - ((uint32_t) ah->ah_sh)+AR5312_RESET),
913 			OS_REG_READ(ah,
914 						(AR5312_RSTIMER_BASE- ((uint32_t) ah->ah_sh) +AR5312_RESET));