dist/ar5212/ar5212_xmit.c

21 #include "ah.h"
45 ar5212UpdateTxTrigLevel(struct ath_hal *ah, HAL_BOOL bIncTrigLevel)
47 	struct ath_hal_5212 *ahp = AH5212(ah);
57 	omask = ath_hal_setInterrupts(ah, ahp->ah_maskReg &~ HAL_INT_GLOBAL);
59 	txcfg = OS_REG_READ(ah, AR_TXCFG);
69 		OS_REG_WRITE(ah, AR_TXCFG,
75 	ath_hal_setInterrupts(ah, omask);
85 ar5212SetTxQueueProps(struct ath_hal *ah, int q, const HAL_TXQ_INFO *qInfo)
87 	struct ath_hal_5212 *ahp = AH5212(ah);
88 	HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps;
91 		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid queue num %u\n",
95 	return ath_hal_setTxQProps(ah, &ahp->ah_txq[q], qInfo);
102 ar5212GetTxQueueProps(struct ath_hal *ah, int q, HAL_TXQ_INFO *qInfo)
104 	struct ath_hal_5212 *ahp = AH5212(ah);
105 	HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps;
109 		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid queue num %u\n",
113 	return ath_hal_getTxQProps(ah, qInfo, &ahp->ah_txq[q]);
120 ar5212SetupTxQueue(struct ath_hal *ah, HAL_TX_QUEUE type,
123 	struct ath_hal_5212 *ahp = AH5212(ah);
125 	HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps;
153 			HALDEBUG(ah, HAL_DEBUG_ANY,
163 			HALDEBUG(ah, HAL_DEBUG_ANY,
169 		HALDEBUG(ah, HAL_DEBUG_ANY,
174 	HALDEBUG(ah, HAL_DEBUG_TXQUEUE, "%s: queue %u\n", __func__, q);
178 		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: tx queue %u already active\n",
194 		(void) ar5212SetTxQueueProps(ah, q, qInfo);
204 setTxQInterrupts(struct ath_hal *ah, HAL_TX_QUEUE_INFO *qi)
206 	struct ath_hal_5212 *ahp = AH5212(ah);
208 	HALDEBUG(ah, HAL_DEBUG_TXQUEUE,
214 	OS_REG_WRITE(ah, AR_IMR_S0,
218 	OS_REG_WRITE(ah, AR_IMR_S1,
222 	OS_REG_RMW_FIELD(ah, AR_IMR_S2,
230 ar5212ReleaseTxQueue(struct ath_hal *ah, u_int q)
232 	struct ath_hal_5212 *ahp = AH5212(ah);
233 	HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps;
237 		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid queue num %u\n",
243 		HALDEBUG(ah, HAL_DEBUG_TXQUEUE, "%s: inactive queue %u\n",
248 	HALDEBUG(ah, HAL_DEBUG_TXQUEUE, "%s: release queue %u\n", __func__, q);
256 	setTxQInterrupts(ah, qi);
267 ar5212ResetTxQueue(struct ath_hal *ah, u_int q)
269 	struct ath_hal_5212 *ahp = AH5212(ah);
270 	HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps;
271 	HAL_CHANNEL_INTERNAL *chan = AH_PRIVATE(ah)->ah_curchan;
276 		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid queue num %u\n",
282 		HALDEBUG(ah, HAL_DEBUG_TXQUEUE, "%s: inactive queue %u\n",
287 	HALDEBUG(ah, HAL_DEBUG_TXQUEUE, "%s: reset queue %u\n", __func__, q);
305 	OS_REG_WRITE(ah, AR_DLCL_IFS(q),
311 	OS_REG_WRITE(ah, AR_DRETRY_LIMIT(q),
326 	if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_OAHU) {
333 		OS_REG_WRITE(ah, AR_QCBRCFG(q),
341 		OS_REG_WRITE(ah, AR_QRDYTIMECFG(q),
346 	OS_REG_WRITE(ah, AR_DCHNTIME(q),
422 			OS_REG_WRITE(ah, AR_QRDYTIMECFG(q), value | AR_Q_RDYTIMECFG_ENA);
431 	OS_REG_WRITE(ah, AR_QMISC(q), qmisc);
432 	OS_REG_WRITE(ah, AR_DMISC(q), dmisc);
442 		OS_REG_WRITE(ah, AR_Q_CBBS, (80 + 2*q));
443 		OS_REG_WRITE(ah, AR_Q_CBBA, qi->tqi_physCompBuf);
444 		OS_REG_WRITE(ah, AR_Q_CBC,  HAL_COMP_BUF_MAX_SIZE/1024);
445 		OS_REG_WRITE(ah, AR_Q0_MISC + 4*q,
446 			     OS_REG_READ(ah, AR_Q0_MISC + 4*q)
480 	setTxQInterrupts(ah, qi);
489 ar5212GetTxDP(struct ath_hal *ah, u_int q)
491 	HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);
492 	return OS_REG_READ(ah, AR_QTXDP(q));
499 ar5212SetTxDP(struct ath_hal *ah, u_int q, uint32_t txdp)
501 	HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);
502 	HALASSERT(AH5212(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
508 	HALASSERT((OS_REG_READ(ah, AR_Q_TXE) & (1 << q)) == 0);
510 	OS_REG_WRITE(ah, AR_QTXDP(q), txdp);
519 ar5212StartTxDma(struct ath_hal *ah, u_int q)
521 	HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);
523 	HALASSERT(AH5212(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
525 	HALDEBUG(ah, HAL_DEBUG_TXQUEUE, "%s: queue %u\n", __func__, q);
528 	HALASSERT((OS_REG_READ(ah, AR_Q_TXD) & (1 << q)) == 0);
530 	OS_REG_WRITE(ah, AR_Q_TXE, 1 << q);
539 ar5212NumTxPending(struct ath_hal *ah, u_int q)
543 	HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);
544 	HALASSERT(AH5212(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
546 	npend = OS_REG_READ(ah, AR_QSTS(q)) & AR_Q_STS_PEND_FR_CNT;
553 		if (OS_REG_READ(ah, AR_Q_TXE) & (1 << q))
563 ar5212StopTxDma(struct ath_hal *ah, u_int q)
568 	HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);
570 	HALASSERT(AH5212(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
572 	OS_REG_WRITE(ah, AR_Q_TXD, 1 << q);
574 		if (ar5212NumTxPending(ah, q) == 0)
580 		HALDEBUG(ah, HAL_DEBUG_ANY,
582 		HALDEBUG(ah, HAL_DEBUG_ANY,
584 		    OS_REG_READ(ah, AR_QSTS(q)), OS_REG_READ(ah, AR_Q_TXE),
585 		    OS_REG_READ(ah, AR_Q_TXD), OS_REG_READ(ah, AR_QCBRCFG(q)));
586 		HALDEBUG(ah, HAL_DEBUG_ANY,
588 		    __func__, OS_REG_READ(ah, AR_QMISC(q)),
589 		    OS_REG_READ(ah, AR_QRDYTIMECFG(q)),
590 		    OS_REG_READ(ah, AR_Q_RDYTIMESHDN));
595 	if (ar5212NumTxPending(ah, q) &&
596 	    (IS_2413(ah) || IS_5413(ah) || IS_2425(ah) || IS_2417(ah))) {
599 		HALDEBUG(ah, HAL_DEBUG_TXQUEUE,
601 		    __func__, ar5212NumTxPending(ah, q), q);
606 			tsfLow = OS_REG_READ(ah, AR_TSF_L32);
607 			OS_REG_WRITE(ah, AR_QUIET2, SM(100, AR_QUIET2_QUIET_PER) |
609 			OS_REG_WRITE(ah, AR_QUIET1, AR_QUIET1_QUIET_ENABLE |
611 			if ((OS_REG_READ(ah, AR_TSF_L32) >> 10) == (tsfLow >> 10)) {
614 			HALDEBUG(ah, HAL_DEBUG_ANY,
620 		OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_CHAN_IDLE);
624 		OS_REG_CLR_BIT(ah, AR_QUIET1, AR_QUIET1_QUIET_ENABLE);
630 		while (ar5212NumTxPending(ah, q)) {
632 				HALDEBUG(ah, HAL_DEBUG_ANY,
640 		OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_CHAN_IDLE);
643 	OS_REG_WRITE(ah, AR_Q_TXD, 0);
663 ar5212SetupTxDesc(struct ath_hal *ah, struct ath_desc *ds,
680 	struct ath_hal_5212 *ahp = AH5212(ah);
718 			HALDEBUG(ah, HAL_DEBUG_ANY,
735 ar5212SetupXTxDesc(struct ath_hal *ah, struct ath_desc *ds,
767 ar5212IntrReqTxDesc(struct ath_hal *ah, struct ath_desc *ds)
779 ar5212FillTxDesc(struct ath_hal *ah, struct ath_desc *ds,
840 ar5212ProcTxDesc(struct ath_hal *ah,
920 ar5212GetTxIntrQueue(struct ath_hal *ah, uint32_t *txqs)
922 	struct ath_hal_5212 *ahp = AH5212(ah);