dist/ar5210/ar5210_misc.c

21 #include "ah.h"
34 ar5210GetMacAddress(struct ath_hal *ah, uint8_t *mac)
36 	struct ath_hal_5210 *ahp = AH5210(ah);
42 ar5210SetMacAddress(struct ath_hal *ah, const uint8_t *mac)
44 	struct ath_hal_5210 *ahp = AH5210(ah);
51 ar5210GetBssIdMask(struct ath_hal *ah, uint8_t *mask)
59 ar5210SetBssIdMask(struct ath_hal *ah, const uint8_t *mask)
68 ar5210EepromRead(struct ath_hal *ah, u_int off, uint16_t *data)
70 	(void) OS_REG_READ(ah, AR_EP_AIR(off));	/* activate read op */
71 	if (!ath_hal_wait(ah, AR_EP_STA,
73 		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: read failed for entry 0x%x\n",
77 	*data = OS_REG_READ(ah, AR_EP_RDATA) & 0xffff;
86 ar5210EepromWrite(struct ath_hal *ah, u_int off, uint16_t data)
96 ar5210SetRegulatoryDomain(struct ath_hal *ah,
101 	if (AH_PRIVATE(ah)->ah_currentRD == regDomain) {
110 	if (ath_hal_eepromGetFlag(ah, AR_EEP_WRITEPROTECT)) {
129 ar5210GetWirelessModes(struct ath_hal *ah)
140 ar5210EnableRfKill(struct ath_hal *ah)
142 	uint16_t rfsilent = AH_PRIVATE(ah)->ah_rfsilent;
154 	ar5210Gpio0SetIntr(ah, select, (ar5210GpioGet(ah, select) == polarity));
161 ar5210GpioCfgOutput(struct ath_hal *ah, uint32_t gpio, HAL_GPIO_MUX_TYPE type)
165 	OS_REG_WRITE(ah, AR_GPIOCR,
166 		  (OS_REG_READ(ah, AR_GPIOCR) &~ AR_GPIOCR_ALL(gpio))
176 ar5210GpioCfgInput(struct ath_hal *ah, uint32_t gpio)
180 	OS_REG_WRITE(ah, AR_GPIOCR,
181 		  (OS_REG_READ(ah, AR_GPIOCR) &~ AR_GPIOCR_ALL(gpio))
191 ar5210GpioSet(struct ath_hal *ah, uint32_t gpio, uint32_t val)
197 	reg =  OS_REG_READ(ah, AR_GPIODO);
201 	OS_REG_WRITE(ah, AR_GPIODO, reg);
209 ar5210GpioGet(struct ath_hal *ah, uint32_t gpio)
212 		uint32_t val = OS_REG_READ(ah, AR_GPIODI);
224 ar5210Gpio0SetIntr(struct ath_hal *ah, u_int gpio, uint32_t ilevel)
226 	uint32_t val = OS_REG_READ(ah, AR_GPIOCR);
237 	OS_REG_WRITE(ah, AR_GPIOCR, val);
240 	ar5210SetInterrupts(ah, AH5210(ah)->ah_maskReg | HAL_INT_GPIO);
247 ar5210SetLedState(struct ath_hal *ah, HAL_LED_STATE state)
251 	val = OS_REG_READ(ah, AR_PCICFG);
266 	OS_REG_WRITE(ah, AR_PCICFG, val);
273 ar5210GetDefAntenna(struct ath_hal *ah)
275 	uint32_t val = OS_REG_READ(ah, AR_STA_ID1);
280 ar5210SetDefAntenna(struct ath_hal *ah, u_int antenna)
282 	uint32_t val = OS_REG_READ(ah, AR_STA_ID1);
288 		OS_REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_DEFAULT_ANTENNA);
293 ar5210GetAntennaSwitch(struct ath_hal *ah)
299 ar5210SetAntennaSwitch(struct ath_hal *ah, HAL_ANT_SETTING settings)
312 ar5210WriteAssocid(struct ath_hal *ah, const uint8_t *bssid, uint16_t assocId)
314 	struct ath_hal_5210 *ahp = AH5210(ah);
318 	OS_REG_WRITE(ah, AR_BSS_ID0, LE_READ_4(ahp->ah_bssid));
319 	OS_REG_WRITE(ah, AR_BSS_ID1, LE_READ_2(ahp->ah_bssid+4) |
322 		OS_REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_NO_PSPOLL);
324 		OS_REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_NO_PSPOLL);
331 ar5210GetTsf64(struct ath_hal *ah)
336 	low1 = OS_REG_READ(ah, AR_TSF_L32);
337 	u32 = OS_REG_READ(ah, AR_TSF_U32);
338 	low2 = OS_REG_READ(ah, AR_TSF_L32);
359 ar5210GetTsf32(struct ath_hal *ah)
361 	return OS_REG_READ(ah, AR_TSF_L32);
368 ar5210ResetTsf(struct ath_hal *ah)
370 	uint32_t val = OS_REG_READ(ah, AR_BEACON);
372 	OS_REG_WRITE(ah, AR_BEACON, val | AR_BEACON_RESET_TSF);
380 ar5210GetRandomSeed(struct ath_hal *ah)
384 	nf = (OS_REG_READ(ah, AR_PHY_BASE + (25 << 2)) >> 19) & 0x1ff;
387 	return (OS_REG_READ(ah, AR_TSF_U32) ^
388 		OS_REG_READ(ah, AR_TSF_L32) ^ nf);
395 ar5210DetectCardPresent(struct ath_hal *ah)
402 	return (AH_PRIVATE(ah)->ah_macRev == (OS_REG_READ(ah, AR_SREV) & 0xff));
409 ar5210UpdateMibCounters(struct ath_hal *ah, HAL_MIB_STATS *stats)
411 	stats->ackrcv_bad += OS_REG_READ(ah, AR_ACK_FAIL);
412 	stats->rts_bad	  += OS_REG_READ(ah, AR_RTS_FAIL);
413 	stats->fcs_bad	  += OS_REG_READ(ah, AR_FCS_FAIL);
414 	stats->rts_good	  += OS_REG_READ(ah, AR_RTS_OK);
415 	stats->beacons	  += OS_REG_READ(ah, AR_BEACON_CNT);
419 ar5210SetSifsTime(struct ath_hal *ah, u_int us)
421 	struct ath_hal_5210 *ahp = AH5210(ah);
423 	if (us > ath_hal_mac_usec(ah, 0x7ff)) {
424 		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad SIFS time %u\n",
430 		OS_REG_RMW_FIELD(ah, AR_IFS0, AR_IFS0_SIFS,
431 		    ath_hal_mac_clks(ah, us));
438 ar5210GetSifsTime(struct ath_hal *ah)
440 	u_int clks = OS_REG_READ(ah, AR_IFS0) & 0x7ff;
441 	return ath_hal_mac_usec(ah, clks);	/* convert from system clocks */
445 ar5210SetSlotTime(struct ath_hal *ah, u_int us)
447 	struct ath_hal_5210 *ahp = AH5210(ah);
449 	if (us < HAL_SLOT_TIME_9 || us > ath_hal_mac_usec(ah, 0xffff)) {
450 		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad slot time %u\n",
456 		OS_REG_WRITE(ah, AR_SLOT_TIME, ath_hal_mac_clks(ah, us));
463 ar5210GetSlotTime(struct ath_hal *ah)
465 	u_int clks = OS_REG_READ(ah, AR_SLOT_TIME) & 0xffff;
466 	return ath_hal_mac_usec(ah, clks);	/* convert from system clocks */
470 ar5210SetAckTimeout(struct ath_hal *ah, u_int us)
472 	struct ath_hal_5210 *ahp = AH5210(ah);
474 	if (us > ath_hal_mac_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
475 		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad ack timeout %u\n",
481 		OS_REG_RMW_FIELD(ah, AR_TIME_OUT,
482 			AR_TIME_OUT_ACK, ath_hal_mac_clks(ah, us));
489 ar5210GetAckTimeout(struct ath_hal *ah)
491 	u_int clks = MS(OS_REG_READ(ah, AR_TIME_OUT), AR_TIME_OUT_ACK);
492 	return ath_hal_mac_usec(ah, clks);	/* convert from system clocks */
496 ar5210GetAckCTSRate(struct ath_hal *ah)
498 	return ((AH5210(ah)->ah_staId1Defaults & AR_STA_ID1_ACKCTS_6MB) == 0);
502 ar5210SetAckCTSRate(struct ath_hal *ah, u_int high)
504 	struct ath_hal_5210 *ahp = AH5210(ah);
507 		OS_REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_ACKCTS_6MB);
510 		OS_REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_ACKCTS_6MB);
517 ar5210SetCTSTimeout(struct ath_hal *ah, u_int us)
519 	struct ath_hal_5210 *ahp = AH5210(ah);
521 	if (us > ath_hal_mac_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
522 		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad cts timeout %u\n",
528 		OS_REG_RMW_FIELD(ah, AR_TIME_OUT,
529 			AR_TIME_OUT_CTS, ath_hal_mac_clks(ah, us));
536 ar5210GetCTSTimeout(struct ath_hal *ah)
538 	u_int clks = MS(OS_REG_READ(ah, AR_TIME_OUT), AR_TIME_OUT_CTS);
539 	return ath_hal_mac_usec(ah, clks);	/* convert from system clocks */
543 ar5210SetDecompMask(struct ath_hal *ah, uint16_t keyidx, int en)
550 ar5210SetCoverageClass(struct ath_hal *ah, uint8_t coverageclass, int now)
558 ar5210AniControl(struct ath_hal *ah, HAL_ANI_CMD cmd, int param)
564 ar5210AniPoll(struct ath_hal *ah, const HAL_NODE_STATS *stats, HAL_CHANNEL *chan)
569 ar5210MibEvent(struct ath_hal *ah, const HAL_NODE_STATS *stats)
576 ar5210GetCapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,
584 		return ath_hal_getcapability(ah, type, capability, result);
589 ar5210SetCapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,
601 		AH_PRIVATE(ah)->ah_diagreg = setting;
603 		AH_PRIVATE(ah)->ah_diagreg = setting & 0x6;	/* ACK+CTS */
605 		OS_REG_WRITE(ah, AR_DIAG_SW, AH_PRIVATE(ah)->ah_diagreg);
610 		return ath_hal_setcapability(ah, type, capability,
616 ar5210GetDiagState(struct ath_hal *ah, int request,
631 		pcicfg = OS_REG_READ(ah, AR_PCICFG);
632 		OS_REG_WRITE(ah, AR_PCICFG, pcicfg | AR_PCICFG_EEPROMSEL);
633 		ok = ath_hal_eepromRead(ah, *(const uint16_t *)args, *result);
634 		OS_REG_WRITE(ah, AR_PCICFG, pcicfg);
640 	return ath_hal_getdiagstate(ah, request,