Lines Matching refs:__u64
140 __u64 bo_size;
142 __u64 alignment;
144 __u64 domains;
146 __u64 domain_flags;
177 __u64 bo_info_ptr;
253 __u64 flags;
278 __u64 flags;
314 __u64 addr;
315 __u64 size;
353 (((__u64)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT)
355 (((__u64)(value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK)
368 __u64 flags;
370 __u64 tiling_info;
384 __u64 addr_ptr;
398 __u64 timeout;
418 __u64 handle;
420 __u64 timeout;
429 __u64 status;
442 __u64 seq_no;
447 __u64 fences;
450 __u64 timeout_ns;
473 __u64 value;
517 __u64 va_address;
519 __u64 offset_in_bo;
521 __u64 map_size;
550 __u64 chunk_data;
560 /** this points to __u64 * which point to cs chunks */
561 __u64 chunks;
565 __u64 handle;
598 __u64 va_start;
614 __u64 handle;
629 __u64 point;
820 __u64 return_pointer;
884 __u64 vram_size;
885 __u64 vram_cpu_accessible_size;
886 __u64 gtt_size;
891 __u64 total_heap_size;
894 __u64 usable_heap_size;
902 __u64 heap_usage;
908 __u64 max_allocation;
946 __u64 max_engine_clock;
947 __u64 max_memory_clock;
958 __u64 ids_flags;
960 __u64 virtual_address_offset;
962 __u64 virtual_address_max;
979 __u64 prim_buf_gpu_addr;
981 __u64 pos_buf_gpu_addr;
983 __u64 cntl_sb_buf_gpu_addr;
985 __u64 param_buf_gpu_addr;
1008 __u64 high_va_offset;
1010 __u64 high_va_max;
1014 __u64 tcc_disabled_mask;
1022 __u64 capabilities_flags;