drm/radeon/radeon_rv770_dpm.c

325 							     struct atom_clock_dividers *dividers,
337 	post_divider = dividers->post_div;
338 	reference_divider = dividers->ref_div;
407 	struct atom_clock_dividers dividers;
415 					     memory_clock, false, &dividers);
419 	if ((dividers.ref_div < 1) || (dividers.ref_div > 5))
424 							 &dividers, &clkf, &clkfrac);
426 	ret = rv770_encode_yclk_post_div(dividers.post_div, &postdiv_yclk);
437 	mpll_ad_func_cntl |= CLKR(encoded_reference_dividers[dividers.ref_div - 1]);
443 	if (dividers.vco_mode)
452 								 &dividers, &clkf, &clkfrac);
456 		ret = rv770_encode_yclk_post_div(dividers.post_div, &postdiv_yclk);
465 		mpll_dq_func_cntl |= CLKR(encoded_reference_dividers[dividers.ref_div - 1]);
471 		if (dividers.vco_mode)
493 	struct atom_clock_dividers dividers;
511 					     engine_clock, false, &dividers);
515 	reference_divider = 1 + dividers.ref_div;
517 	if (dividers.enable_post_div)
518 		post_divider = (0x0f & (dividers.post_div >> 4)) + (0x0f & dividers.post_div) + 2;
526 	if (dividers.enable_post_div)
531 	spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
532 	spll_func_cntl |= SPLL_HILEN((dividers.post_div >> 4) & 0xf);
533 	spll_func_cntl |= SPLL_LOLEN(dividers.post_div & 0xf);
2351 	struct atom_clock_dividers dividers;
2379 					     0, false, &dividers);
2381 		pi->ref_div = dividers.ref_div + 1;