drm/radeon/radeon_rv6xx_dpm.c

447 	pi->hw.sclks[R600_POWER_LEVEL_HIGH] =
452 	pi->hw.high_sclk_index = R600_POWER_LEVEL_HIGH;
462 	pi->hw.mclks[R600_POWER_LEVEL_HIGH] =
469 	pi->hw.high_mclk_index = R600_POWER_LEVEL_HIGH;
491 	pi->hw.vddc[R600_POWER_LEVEL_HIGH] = state->high.vddc;
497 	pi->hw.backbias[R600_POWER_LEVEL_HIGH] =
504 	pi->hw.pcie_gen2[R600_POWER_LEVEL_HIGH] =
511 	pi->hw.high_vddc_index = R600_POWER_LEVEL_HIGH;
593 					     pi->hw.sclks[R600_POWER_LEVEL_HIGH],
594 					     R600_POWER_LEVEL_HIGH);
806 	if (pi->hw.sclks[R600_POWER_LEVEL_HIGH] <
808 		high_clock = pi->hw.sclks[R600_POWER_LEVEL_HIGH];
817 		     STATE2(64 * high_clock / pi->hw.sclks[R600_POWER_LEVEL_HIGH]) |
818 		     STATE3(64 * high_clock / pi->hw.sclks[R600_POWER_LEVEL_HIGH]));
827 							  pi->hw.sclks[R600_POWER_LEVEL_HIGH])) |
829 							  pi->hw.sclks[R600_POWER_LEVEL_HIGH])));
1161 	r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_HIGH,
1163 	r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_HIGH,
1165 	r600_power_level_set_eng_clock_index(rdev, R600_POWER_LEVEL_HIGH,
1168 	r600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_HIGH,
1171 	r600_power_level_set_pcie_gen2(rdev, R600_POWER_LEVEL_HIGH,
1172 				       pi->hw.pcie_gen2[R600_POWER_LEVEL_HIGH]);
1345 		r600_power_level_enable(rdev, R600_POWER_LEVEL_HIGH, true);
1484 		rv6xx_enable_engine_spread_spectrum(rdev, R600_POWER_LEVEL_HIGH, false);
1599 	r600_power_level_enable(rdev, R600_POWER_LEVEL_HIGH, true);
1635 	r600_power_level_enable(rdev, R600_POWER_LEVEL_HIGH, false);
1680 	r600_power_level_enable(rdev, R600_POWER_LEVEL_HIGH, false);
2154 	r600_power_level_enable(rdev, R600_POWER_LEVEL_HIGH, false);