Lines Matching refs:sclk_high
415 if (current_state->sclk_low == current_state->sclk_high)
440 if ((new_state->sclk_high == old_state->sclk_high) &&
450 new_state->sclk_high, false, &max_dividers);
455 old_state->sclk_high, false, ¤t_max_dividers);
487 if ((new_state->sclk_high == old_state->sclk_high) &&
505 if ((new_state->sclk_high == old_state->sclk_high) &&
509 if (new_state->sclk_high == new_state->sclk_low)
580 if (new_state->sclk_high >= current_state->sclk_high)
597 if (new_state->sclk_high < current_state->sclk_high)
765 ps->sclk_high = sclk;
789 ps->sclk_high = rdev->clock.default_sclk;
955 ps->sclk_high, ps->max_voltage);
977 return requested_state->sclk_high;
1009 ps->sclk_high, ps->max_voltage);
1052 ps->sclk_high, false, ÷rs);
1071 if (ps->sclk_high != ps->sclk_low) {