Lines Matching defs:tv_uv_adr
350 static uint16_t radeon_get_htiming_tables_addr(uint32_t tv_uv_adr)
354 switch ((tv_uv_adr & RADEON_HCODE_TABLE_SEL_MASK) >> RADEON_HCODE_TABLE_SEL_SHIFT) {
359 h_table = ((tv_uv_adr & RADEON_TABLE1_BOT_ADR_MASK) >> RADEON_TABLE1_BOT_ADR_SHIFT) * 2;
362 h_table = ((tv_uv_adr & RADEON_TABLE3_TOP_ADR_MASK) >> RADEON_TABLE3_TOP_ADR_SHIFT) * 2;
371 static uint16_t radeon_get_vtiming_tables_addr(uint32_t tv_uv_adr)
375 switch ((tv_uv_adr & RADEON_VCODE_TABLE_SEL_MASK) >> RADEON_VCODE_TABLE_SEL_SHIFT) {
377 v_table = ((tv_uv_adr & RADEON_MAX_UV_ADR_MASK) >> RADEON_MAX_UV_ADR_SHIFT) * 2 + 1;
380 v_table = ((tv_uv_adr & RADEON_TABLE1_BOT_ADR_MASK) >> RADEON_TABLE1_BOT_ADR_SHIFT) * 2 + 1;
383 v_table = ((tv_uv_adr & RADEON_TABLE3_TOP_ADR_MASK) >> RADEON_TABLE3_TOP_ADR_SHIFT) * 2 + 1;
401 WREG32(RADEON_TV_UV_ADR, tv_dac->tv.tv_uv_adr);
402 h_table = radeon_get_htiming_tables_addr(tv_dac->tv.tv_uv_adr);
403 v_table = radeon_get_vtiming_tables_addr(tv_dac->tv.tv_uv_adr);
717 tv_dac->tv.tv_uv_adr = 0xc8;