drm/radeon/radeon_legacy_tv.c

248 	struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
261 	if (tv_dac->tv_std == TV_STD_NTSC ||
262 	    tv_dac->tv_std == TV_STD_NTSC_J ||
263 	    tv_dac->tv_std == TV_STD_PAL_M) {
396 	struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
401 	WREG32(RADEON_TV_UV_ADR, tv_dac->tv.tv_uv_adr);
402 	h_table = radeon_get_htiming_tables_addr(tv_dac->tv.tv_uv_adr);
403 	v_table = radeon_get_vtiming_tables_addr(tv_dac->tv.tv_uv_adr);
406 		tmp = ((uint32_t)tv_dac->tv.h_code_timing[i] << 14) | ((uint32_t)tv_dac->tv.h_code_timing[i+1]);
408 		if (tv_dac->tv.h_code_timing[i] == 0 || tv_dac->tv.h_code_timing[i + 1] == 0)
412 		tmp = ((uint32_t)tv_dac->tv.v_code_timing[i+1] << 14) | ((uint32_t)tv_dac->tv.v_code_timing[i]);
414 		if (tv_dac->tv.v_code_timing[i] == 0 || tv_dac->tv.v_code_timing[i + 1] == 0)
423 	struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
424 	WREG32(RADEON_TV_FRESTART, tv_dac->tv.frestart);
425 	WREG32(RADEON_TV_HRESTART, tv_dac->tv.hrestart);
426 	WREG32(RADEON_TV_VRESTART, tv_dac->tv.vrestart);
432 	struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
447 	if (tv_dac->tv_std == TV_STD_NTSC ||
448 	    tv_dac->tv_std == TV_STD_NTSC_J ||
449 	    tv_dac->tv_std == TV_STD_PAL_M ||
450 	    tv_dac->tv_std == TV_STD_PAL_60)
456 	h_offset = tv_dac->h_pos * H_POS_UNIT;
458 	if (tv_dac->tv_std == TV_STD_NTSC ||
459 	    tv_dac->tv_std == TV_STD_NTSC_J ||
460 	    tv_dac->tv_std == TV_STD_PAL_M) {
472 	h_changed = (p1 != tv_dac->tv.h_code_timing[H_TABLE_POS1] ||
473 		     p2 != tv_dac->tv.h_code_timing[H_TABLE_POS2]);
475 	tv_dac->tv.h_code_timing[H_TABLE_POS1] = p1;
476 	tv_dac->tv.h_code_timing[H_TABLE_POS2] = p2;
487 	if (tv_dac->tv_std == TV_STD_NTSC ||
488 	    tv_dac->tv_std == TV_STD_NTSC_J ||
489 	    tv_dac->tv_std == TV_STD_PAL_M ||
490 	    tv_dac->tv_std == TV_STD_PAL_60)
491 		v_offset = ((int)(v_total * h_total) * 2 * tv_dac->v_pos) / (int)(NTSC_TV_LINES_PER_FRAME);
493 		v_offset = ((int)(v_total * h_total) * 2 * tv_dac->v_pos) / (int)(PAL_TV_LINES_PER_FRAME);
498 		  const_ptr->def_restart, tv_dac->h_pos, tv_dac->v_pos, p1, p2, restart);
500 	tv_dac->tv.hrestart = restart % h_total;
502 	tv_dac->tv.vrestart = restart % v_total;
504 	tv_dac->tv.frestart = restart % f_total;
507 		  (unsigned)tv_dac->tv.frestart,
508 		  (unsigned)tv_dac->tv.vrestart,
509 		  (unsigned)tv_dac->tv.hrestart);
512 	if (tv_dac->tv_std == TV_STD_NTSC ||
513 	    tv_dac->tv_std == TV_STD_NTSC_J ||
514 	    tv_dac->tv_std == TV_STD_PAL_M)
516 			      (tv_dac->h_size * (int)(NTSC_TV_H_SIZE_UNIT) + (int)(NTSC_TV_ZERO_H_SIZE)));
519 			      (tv_dac->h_size * (int)(PAL_TV_H_SIZE_UNIT) + (int)(PAL_TV_ZERO_H_SIZE)));
521 	tv_dac->tv.timing_cntl = (tv_dac->tv.timing_cntl & ~RADEON_H_INC_MASK) |
524 	DRM_DEBUG_KMS("compute_restart: h_size = %d h_inc = %d\n", tv_dac->h_size, h_inc);
536 	struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
565 	if (tv_dac->tv_std == TV_STD_NTSC ||
566 	    tv_dac->tv_std == TV_STD_NTSC_J)
575 	if (tv_dac->tv_std == TV_STD_NTSC ||
576 	    tv_dac->tv_std == TV_STD_NTSC_J) {
581 	} else if (tv_dac->tv_std == TV_STD_SCART_PAL) {
610 	if (tv_dac->tv_std == TV_STD_NTSC ||
611 	    tv_dac->tv_std == TV_STD_NTSC_J ||
612 	    tv_dac->tv_std == TV_STD_PAL_M ||
613 	    tv_dac->tv_std == TV_STD_PAL_60)
633 	if (tv_dac->tv_std == TV_STD_NTSC ||
634 	    tv_dac->tv_std == TV_STD_NTSC_J ||
635 	    tv_dac->tv_std == TV_STD_PAL_M ||
636 	    tv_dac->tv_std == TV_STD_PAL_60) {
670 	tv_dac->tv.timing_cntl = tmp;
672 	if (tv_dac->tv_std == TV_STD_NTSC ||
673 	    tv_dac->tv_std == TV_STD_NTSC_J ||
674 	    tv_dac->tv_std == TV_STD_PAL_M ||
675 	    tv_dac->tv_std == TV_STD_PAL_60)
676 		tv_dac_cntl = tv_dac->ntsc_tvdac_adj;
678 		tv_dac_cntl = tv_dac->pal_tvdac_adj;
682 	if (tv_dac->tv_std == TV_STD_NTSC ||
683 	    tv_dac->tv_std == TV_STD_NTSC_J)
688 	if (tv_dac->tv_std == TV_STD_NTSC ||
689 	    tv_dac->tv_std == TV_STD_NTSC_J) {
717 	tv_dac->tv.tv_uv_adr = 0xc8;
719 	if (tv_dac->tv_std == TV_STD_NTSC ||
720 	    tv_dac->tv_std == TV_STD_NTSC_J ||
721 	    tv_dac->tv_std == TV_STD_PAL_M ||
722 	    tv_dac->tv_std == TV_STD_PAL_60) {
733 		if ((tv_dac->tv.h_code_timing[i] = hor_timing[i]) == 0)
738 		if ((tv_dac->tv.v_code_timing[i] = vert_timing[i]) == 0)
808 	WREG32(RADEON_TV_TIMING_CNTL, tv_dac->tv.timing_cntl);