drm/radeon/radeon_cypress_dpm.c

128 	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
131 		if (eg_pi->light_sleep) {
156 		if (eg_pi->light_sleep) {
181 	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
203 		if (eg_pi->mcls) {
310 	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
322 		eg_pi->pcie_performance_request_registered = true;
325 		   eg_pi->pcie_performance_request_registered) {
326 		eg_pi->pcie_performance_request_registered = false;
662 	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
665 		voltage->index = eg_pi->mvdd_high_index;
671 		voltage->index = eg_pi->mvdd_low_index;
674 		voltage->index = eg_pi->mvdd_high_index;
687 	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
704 	    !eg_pi->uvd_enabled) {
706 		if (eg_pi->sclk_deep_sleep)
716 		if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold)
728 			dll_state_on = eg_pi->dll_default_on;
748 					     &eg_pi->vddc_voltage_table,
754 	if (eg_pi->vddci_control) {
756 						     &eg_pi->vddci_voltage_table,
773 	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
804 	if (eg_pi->dynamic_ac_timing) {
837 	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
840 	for (i = 0; i < eg_pi->mc_reg_table.num_entries; i++) {
842 		    eg_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)
846 	if ((i == eg_pi->mc_reg_table.num_entries) && (i > 0))
849 	cypress_convert_mc_registers(&eg_pi->mc_reg_table.mc_reg_table_entry[i],
851 				     eg_pi->mc_reg_table.last,
852 				     eg_pi->mc_reg_table.valid_flag);
894 	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
900 	address = eg_pi->mc_reg_table_start +
956 	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
959 	for (i = 0, j = 0; j < eg_pi->mc_reg_table.last; j++) {
960 		if (eg_pi->mc_reg_table.valid_flag & (1 << j)) {
962 				cpu_to_be16(eg_pi->mc_reg_table.mc_reg_address[j].s0);
964 				cpu_to_be16(eg_pi->mc_reg_table.mc_reg_address[j].s1);
974 	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
977 	eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_RAS_TIMING_LP >> 2;
978 	eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_RAS_TIMING >> 2;
981 	eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_CAS_TIMING_LP >> 2;
982 	eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_CAS_TIMING >> 2;
985 	eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_MISC_TIMING_LP >> 2;
986 	eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_MISC_TIMING >> 2;
989 	eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_MISC_TIMING2_LP >> 2;
990 	eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_MISC_TIMING2 >> 2;
993 	eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_RD_CTL_D0_LP >> 2;
994 	eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_RD_CTL_D0 >> 2;
997 	eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_RD_CTL_D1_LP >> 2;
998 	eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_RD_CTL_D1 >> 2;
1001 	eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_WR_CTL_D0_LP >> 2;
1002 	eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_WR_CTL_D0 >> 2;
1005 	eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_WR_CTL_D1_LP >> 2;
1006 	eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_WR_CTL_D1 >> 2;
1009 	eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
1010 	eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_PMG_CMD_EMRS >> 2;
1013 	eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2;
1014 	eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_PMG_CMD_MRS >> 2;
1017 	eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
1018 	eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_PMG_CMD_MRS1 >> 2;
1021 	eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_MISC1 >> 2;
1022 	eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_MISC1 >> 2;
1025 	eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_RESERVE_M >> 2;
1026 	eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_RESERVE_M >> 2;
1029 	eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_MISC3 >> 2;
1030 	eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_MISC3 >> 2;
1033 	eg_pi->mc_reg_table.last = (u8)i;
1039 	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1042 	for (i = 0; i < eg_pi->mc_reg_table.last; i++)
1044 			RREG32(eg_pi->mc_reg_table.mc_reg_address[i].s1 << 2);
1051 	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1055 		eg_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max =
1059 							 &eg_pi->mc_reg_table.mc_reg_table_entry[i]);
1062 	eg_pi->mc_reg_table.num_entries = range_table->num_entries;
1063 	eg_pi->mc_reg_table.valid_flag = 0;
1065 	for (i = 0; i < eg_pi->mc_reg_table.last; i++) {
1067 			if (eg_pi->mc_reg_table.mc_reg_table_entry[j-1].mc_data[i] !=
1068 			    eg_pi->mc_reg_table.mc_reg_table_entry[j].mc_data[i]) {
1069 				eg_pi->mc_reg_table.valid_flag |= (1 << i);
1173 	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1177 	for (i = 0; i < eg_pi->mc_reg_table.last; i++) {
1178 		value = RREG32(eg_pi->mc_reg_table.mc_reg_address[i].s1 << 2);
1179 		WREG32(eg_pi->mc_reg_table.mc_reg_address[i].s0 << 2, value);
1232 	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1234 	voltage->index = eg_pi->mvdd_high_index;
1246 	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1289 				       &eg_pi->vddc_voltage_table,
1293 	if (eg_pi->vddci_control)
1295 					       &eg_pi->vddci_voltage_table,
1340 	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1366 					       &eg_pi->vddc_voltage_table,
1382 					       &eg_pi->vddc_voltage_table,
1388 	if (eg_pi->acpi_vddci) {
1389 		if (eg_pi->vddci_control) {
1391 						       &eg_pi->vddci_voltage_table,
1392 						       eg_pi->acpi_vddci,
1464 	if (eg_pi->dynamic_ac_timing)
1491 	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1495 					    &eg_pi->vddc_voltage_table);
1499 	if (eg_pi->vddc_voltage_table.count > MAX_NO_VREG_STEPS)
1501 							      &eg_pi->vddc_voltage_table);
1503 	if (eg_pi->vddci_control) {
1505 						    &eg_pi->vddci_voltage_table);
1509 		if (eg_pi->vddci_voltage_table.count > MAX_NO_VREG_STEPS)
1511 								      &eg_pi->vddci_voltage_table);
1533 	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1536 	if (eg_pi->vddc_voltage_table.count) {
1538 						   &eg_pi->vddc_voltage_table,
1543 			cpu_to_be32(eg_pi->vddc_voltage_table.mask_low);
1545 		for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) {
1547 			    eg_pi->vddc_voltage_table.entries[i].value) {
1554 	if (eg_pi->vddci_voltage_table.count) {
1556 						   &eg_pi->vddci_voltage_table,
1561 			cpu_to_be32(eg_pi->vddci_voltage_table.mask_low);
1579 	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1585 		eg_pi->mvdd_high_index = 0;
1586 		eg_pi->mvdd_low_index = 1;
1592 		eg_pi->mvdd_high_index = 1;
1594 		eg_pi->mvdd_high_index = 0;
1596 	eg_pi->mvdd_low_index =
1597 		(eg_pi->mvdd_high_index == 0) ? 1 : 0;
1673 	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1686 	cypress_convert_mc_registers(&eg_pi->mc_reg_table.mc_reg_table_entry[0],
1687 				     &mc_reg_table.data[1], eg_pi->mc_reg_table.last,
1688 				     eg_pi->mc_reg_table.valid_flag);
1692 	return rv770_copy_bytes_to_smc(rdev, eg_pi->mc_reg_table_start,
1700 	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1729 	eg_pi->mc_reg_table_start = (u16)tmp;
1791 	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1798 	if (eg_pi->pcie_performance_request)
1799 		eg_pi->pcie_performance_request_registered = false;
1801 	if (eg_pi->pcie_performance_request)
1812 	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1839 	if (eg_pi->dynamic_ac_timing) {
1844 			eg_pi->dynamic_ac_timing = false;
1885 	if (eg_pi->dynamic_ac_timing) {
1904 	if (eg_pi->memory_transition)
1923 	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1954 	if (eg_pi->dynamic_ac_timing)
1962 	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1972 	if (eg_pi->pcie_performance_request)
1986 	if (eg_pi->dynamic_ac_timing) {
2008 	if (eg_pi->pcie_performance_request)
2030 	struct evergreen_power_info *eg_pi;
2034 	eg_pi = kzalloc(sizeof(struct evergreen_power_info), GFP_KERNEL);
2035 	if (eg_pi == NULL)
2037 	rdev->pm.dpm.priv = eg_pi;
2038 	pi = &eg_pi->rv7xx;
2042 	eg_pi->ulv.supported = false;
2044 	eg_pi->acpi_vddci = 0;
2070 	eg_pi->mclk_edc_wr_enable_threshold = 40000;
2083 	eg_pi->vddci_control =
2102 	eg_pi->ls_clock_gating = false;
2103 	eg_pi->sclk_deep_sleep = false;
2121 	eg_pi->dynamic_ac_timing = true;
2122 	eg_pi->abm = true;
2123 	eg_pi->mcls = true;
2124 	eg_pi->light_sleep = true;
2125 	eg_pi->memory_transition = true;
2127 	eg_pi->pcie_performance_request =
2130 	eg_pi->pcie_performance_request = false;
2136 		eg_pi->dll_default_on = true;
2138 		eg_pi->dll_default_on = false;
2140 	eg_pi->sclk_deep_sleep = false;