drm/radeon/radeon_clocks.c

114 	struct radeon_pll *p1pll = &rdev->clock.p1pll;
126 	p1pll->reference_freq = p2pll->reference_freq = (*val) / 10;
127 	p1pll->reference_div = RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
128 	if (p1pll->reference_div < 2)
129 		p1pll->reference_div = 12;
130 	p2pll->reference_div = p1pll->reference_div;
134 		p1pll->pll_in_min = 100;
135 		p1pll->pll_in_max = 1350;
136 		p1pll->pll_out_min = 20000;
137 		p1pll->pll_out_max = 50000;
143 		p1pll->pll_in_min = 40;
144 		p1pll->pll_in_max = 500;
145 		p1pll->pll_out_min = 12500;
146 		p1pll->pll_out_max = 35000;
155 	spll->reference_freq = mpll->reference_freq = p1pll->reference_freq;
188 	struct radeon_pll *p1pll = &rdev->clock.p1pll;
203 		if (p1pll->reference_div < 2) {
207 					p1pll->reference_div =
210 					p1pll->reference_div = tmp & RADEON_PPLL_REF_DIV_MASK;
211 				if (p1pll->reference_div < 2)
212 					p1pll->reference_div = 12;
214 				p1pll->reference_div = 12;
236 				p1pll->reference_freq = 1432;
241 				p1pll->reference_freq = 2700;
246 			p1pll->reference_div =
248 			if (p1pll->reference_div < 2)
249 				p1pll->reference_div = 12;
250 			p2pll->reference_div = p1pll->reference_div;
253 				p1pll->pll_in_min = 100;
254 				p1pll->pll_in_max = 1350;
255 				p1pll->pll_out_min = 20000;
256 				p1pll->pll_out_max = 50000;
262 				p1pll->pll_in_min = 40;
263 				p1pll->pll_in_max = 500;
264 				p1pll->pll_out_min = 12500;
265 				p1pll->pll_out_max = 35000;
285 		p1pll->min_post_div = 2;
286 		p1pll->max_post_div = 0x7f;
287 		p1pll->min_frac_feedback_div = 0;
288 		p1pll->max_frac_feedback_div = 9;
294 		p1pll->min_post_div = 1;
295 		p1pll->max_post_div = 16;
296 		p1pll->min_frac_feedback_div = 0;
297 		p1pll->max_frac_feedback_div = 0;
315 	p1pll->min_ref_div = 2;
316 	p1pll->max_ref_div = 0x3ff;
317 	p1pll->min_feedback_div = 4;
318 	p1pll->max_feedback_div = 0x7ff;
319 	p1pll->best_vco = 0;