drm/radeon/radeon_atombios_crtc.c

1160 	uint32_t fb_format, fb_pitch_pixels, tiling_flags;
1204 		fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) |
1209 		fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1217 		fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1225 		fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1232 		fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1240 		fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
1248 		fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
1258 		fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
1268 		fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
1325 			fb_format |= EVERGREEN_GRPH_NUM_BANKS(num_banks);
1335 				fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_4_BANK);
1339 				fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_8_BANK);
1342 				fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_16_BANK);
1347 		fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1);
1348 		fb_format |= EVERGREEN_GRPH_TILE_SPLIT(tile_split);
1349 		fb_format |= EVERGREEN_GRPH_BANK_WIDTH(bankw);
1350 		fb_format |= EVERGREEN_GRPH_BANK_HEIGHT(bankh);
1351 		fb_format |= EVERGREEN_GRPH_MACRO_TILE_ASPECT(mtaspect);
1354 			fb_format |= CIK_GRPH_MICRO_TILE_MODE(CIK_DISPLAY_MICRO_TILING);
1357 		fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1);
1365 		fb_format |= CIK_GRPH_PIPE_CONFIG(pipe_config);
1368 		fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P8_32x32_8x16);
1372 		fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P4_8x16);
1410 	WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
1483 	uint32_t fb_format, fb_pitch_pixels, tiling_flags;
1526 		fb_format =
1532 		fb_format =
1540 		fb_format =
1548 		fb_format =
1557 		fb_format =
1566 		fb_format =
1577 		fb_format =
1585 			fb_format |= AVIVO_D1GRPH_SWAP_RB;
1598 			fb_format |= R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1;
1600 			fb_format |= R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1;
1603 			fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE;
1606 			fb_format |= AVIVO_D1GRPH_TILED;
1632 	WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);