Lines Matching refs:GPCPLL_CFG
266 nvkm_mask(device, GPCPLL_CFG, GPCPLL_CFG_ENABLE, GPCPLL_CFG_ENABLE);
267 nvkm_rd32(device, GPCPLL_CFG);
270 val = nvkm_rd32(device, GPCPLL_CFG);
273 nvkm_wr32(device, GPCPLL_CFG, val);
277 if (nvkm_wait_usec(device, 300, GPCPLL_CFG, GPCPLL_CFG_LOCK,
296 nvkm_mask(device, GPCPLL_CFG, GPCPLL_CFG_ENABLE, 0);
297 nvkm_rd32(device, GPCPLL_CFG);
566 nvkm_mask(device, GPCPLL_CFG, GPCPLL_CFG_IDDQ, 1);
578 nvkm_mask(device, GPCPLL_CFG, GPCPLL_CFG_IDDQ, 0);
579 nvkm_rd32(device, GPCPLL_CFG);