drm/i915/intel_pm.c

1079 static int g4x_plane_fifo_size(enum plane_id plane_id, int level)
1095 	switch (plane_id) {
1103 		MISSING_CASE(plane_id);
1183 				 int level, enum plane_id plane_id, u16 value)
1191 		dirty |= raw->plane[plane_id] != value;
1192 		raw->plane[plane_id] = value;
1227 	enum plane_id plane_id = plane->id;
1232 		dirty |= g4x_raw_plane_wm_set(crtc_state, 0, plane_id, 0);
1233 		if (plane_id == PLANE_PRIMARY)
1243 		max_wm = g4x_plane_fifo_size(plane_id, level);
1248 		dirty |= raw->plane[plane_id] != wm;
1249 		raw->plane[plane_id] = wm;
1251 		if (plane_id != PLANE_PRIMARY ||
1256 					raw->plane[plane_id]);
1271 	dirty |= g4x_raw_plane_wm_set(crtc_state, level, plane_id, USHRT_MAX);
1273 	if (plane_id == PLANE_PRIMARY)
1281 			    crtc_state->wm.g4x.raw[G4X_WM_LEVEL_NORMAL].plane[plane_id],
1282 			    crtc_state->wm.g4x.raw[G4X_WM_LEVEL_SR].plane[plane_id],
1283 			    crtc_state->wm.g4x.raw[G4X_WM_LEVEL_HPLL].plane[plane_id]);
1285 		if (plane_id == PLANE_PRIMARY)
1296 				      enum plane_id plane_id, int level)
1300 	return raw->plane[plane_id] <= g4x_plane_fifo_size(plane_id, level);
1321 		enum plane_id plane_id;
1323 		for_each_plane_id_on_crtc(crtc, plane_id)
1324 			wm_state->wm.plane[plane_id] = USHRT_MAX;
1354 	enum plane_id plane_id;
1377 	for_each_plane_id_on_crtc(crtc, plane_id)
1378 		wm_state->wm.plane[plane_id] = raw->plane[plane_id];
1441 	enum plane_id plane_id;
1457 	for_each_plane_id_on_crtc(crtc, plane_id) {
1458 		intermediate->wm.plane[plane_id] =
1459 			max(optimal->wm.plane[plane_id],
1460 			    active->wm.plane[plane_id]);
1462 		WARN_ON(intermediate->wm.plane[plane_id] >
1463 			g4x_plane_fifo_size(plane_id, G4X_WM_LEVEL_NORMAL));
1687 	enum plane_id plane_id;
1711 	for_each_plane_id_on_crtc(crtc, plane_id) {
1714 		if ((active_planes & BIT(plane_id)) == 0) {
1715 			fifo_state->plane[plane_id] = 0;
1719 		rate = raw->plane[plane_id];
1720 		fifo_state->plane[plane_id] = fifo_size * rate / total_rate;
1721 		fifo_left -= fifo_state->plane[plane_id];
1732 	for_each_plane_id_on_crtc(crtc, plane_id) {
1738 		if ((active_planes & BIT(plane_id)) == 0)
1742 		fifo_state->plane[plane_id] += plane_extra;
1764 		enum plane_id plane_id;
1766 		for_each_plane_id_on_crtc(crtc, plane_id)
1767 			wm_state->wm[level].plane[plane_id] = USHRT_MAX;
1787 				 int level, enum plane_id plane_id, u16 value)
1796 		dirty |= raw->plane[plane_id] != value;
1797 		raw->plane[plane_id] = value;
1808 	enum plane_id plane_id = plane->id;
1814 		dirty |= vlv_raw_plane_wm_set(crtc_state, 0, plane_id, 0);
1821 		int max_wm = plane_id == PLANE_CURSOR ? 63 : 511;
1826 		dirty |= raw->plane[plane_id] != wm;
1827 		raw->plane[plane_id] = wm;
1831 	dirty |= vlv_raw_plane_wm_set(crtc_state, level, plane_id, USHRT_MAX);
1838 			    crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM2].plane[plane_id],
1839 			    crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM5].plane[plane_id],
1840 			    crtc_state->wm.vlv.raw[VLV_WM_LEVEL_DDR_DVFS].plane[plane_id]);
1846 				      enum plane_id plane_id, int level)
1853 	return raw->plane[plane_id] <= fifo_state->plane[plane_id];
1879 	enum plane_id plane_id;
1939 		for_each_plane_id_on_crtc(crtc, plane_id) {
1940 			wm_state->wm[level].plane[plane_id] =
1941 				vlv_invert_wm_value(raw->plane[plane_id],
1942 						    fifo_state->plane[plane_id]);
2093 		enum plane_id plane_id;
2095 		for_each_plane_id_on_crtc(crtc, plane_id) {
2096 			intermediate->wm[level].plane[plane_id] =
2097 				min(optimal->wm[level].plane[plane_id],
2098 				    active->wm[level].plane[plane_id]);
4041 			   const enum plane_id plane_id,
4049 	if (plane_id == PLANE_CURSOR) {
4055 	val = I915_READ(PLANE_CTL(pipe, plane_id));
4064 		val = I915_READ(PLANE_BUF_CFG(pipe, plane_id));
4067 		val = I915_READ(PLANE_BUF_CFG(pipe, plane_id));
4068 		val2 = I915_READ(PLANE_NV12_BUF_CFG(pipe, plane_id));
4087 	enum plane_id plane_id;
4094 	for_each_plane_id_on_crtc(crtc, plane_id)
4096 					   plane_id,
4097 					   &ddb_y[plane_id],
4098 					   &ddb_uv[plane_id]);
4217 		enum plane_id plane_id = plane->id;
4222 		plane_data_rate[plane_id] = rate;
4227 		uv_plane_data_rate[plane_id] = rate;
4247 		enum plane_id plane_id = plane->id;
4252 			plane_data_rate[plane_id] = rate;
4255 			enum plane_id y_plane_id;
4274 			plane_data_rate[plane_id] = rate;
4295 	enum plane_id plane_id;
4347 		for_each_plane_id_on_crtc(intel_crtc, plane_id) {
4349 				&crtc_state->wm.skl.optimal.planes[plane_id];
4351 			if (plane_id == PLANE_CURSOR) {
4383 	for_each_plane_id_on_crtc(intel_crtc, plane_id) {
4385 			&crtc_state->wm.skl.optimal.planes[plane_id];
4389 		if (plane_id == PLANE_CURSOR)
4399 		rate = plane_data_rate[plane_id];
4403 		total[plane_id] = wm->wm[level].min_ddb_alloc + extra;
4410 		rate = uv_plane_data_rate[plane_id];
4414 		uv_total[plane_id] = wm->uv_wm[level].min_ddb_alloc + extra;
4422 	for_each_plane_id_on_crtc(intel_crtc, plane_id) {
4424 			&crtc_state->wm.skl.plane_ddb_y[plane_id];
4426 			&crtc_state->wm.skl.plane_ddb_uv[plane_id];
4428 		if (plane_id == PLANE_CURSOR)
4432 		WARN_ON(INTEL_GEN(dev_priv) >= 11 && uv_total[plane_id]);
4435 		if (total[plane_id]) {
4437 			start += total[plane_id];
4441 		if (uv_total[plane_id]) {
4443 			start += uv_total[plane_id];
4455 		for_each_plane_id_on_crtc(intel_crtc, plane_id) {
4457 				&crtc_state->wm.skl.optimal.planes[plane_id];
4471 			if (wm->wm[level].min_ddb_alloc > total[plane_id] ||
4472 			    wm->uv_wm[level].min_ddb_alloc > uv_total[plane_id])
4492 	for_each_plane_id_on_crtc(intel_crtc, plane_id) {
4494 			&crtc_state->wm.skl.optimal.planes[plane_id];
4496 		if (wm->trans_wm.plane_res_b >= total[plane_id])
4935 				     enum plane_id plane_id, int color_plane)
4937 	struct skl_plane_wm *wm = &crtc_state->wm.skl.optimal.planes[plane_id];
4954 				 enum plane_id plane_id)
4956 	struct skl_plane_wm *wm = &crtc_state->wm.skl.optimal.planes[plane_id];
4978 	enum plane_id plane_id = plane->id;
4985 					plane_id, 0);
4991 					    plane_id);
5002 	enum plane_id plane_id = to_intel_plane(plane_state->uapi.plane)->id;
5011 		enum plane_id y_plane_id = plane_state->planar_linked_plane->id;
5023 						plane_id, 1);
5028 						plane_id, 0);
5097 	enum plane_id plane_id = plane->id;
5100 		&crtc_state->wm.skl.optimal.planes[plane_id];
5102 		&crtc_state->wm.skl.plane_ddb_y[plane_id];
5104 		&crtc_state->wm.skl.plane_ddb_uv[plane_id];
5107 		skl_write_wm_level(dev_priv, PLANE_WM(pipe, plane_id, level),
5110 	skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane_id),
5115 				    PLANE_BUF_CFG(pipe, plane_id), ddb_y);
5123 			    PLANE_BUF_CFG(pipe, plane_id), ddb_y);
5125 			    PLANE_NV12_BUF_CFG(pipe, plane_id), ddb_uv);
5133 	enum plane_id plane_id = plane->id;
5136 		&crtc_state->wm.skl.optimal.planes[plane_id];
5138 		&crtc_state->wm.skl.plane_ddb_y[plane_id];
5178 	enum plane_id plane_id;
5180 	for_each_plane_id_on_crtc(crtc, plane_id) {
5182 					 &wm1->planes[plane_id],
5183 					 &wm2->planes[plane_id]))
5222 		enum plane_id plane_id = plane->id;
5224 		if (skl_ddb_entry_equal(&old_crtc_state->wm.skl.plane_ddb_y[plane_id],
5225 					&new_crtc_state->wm.skl.plane_ddb_y[plane_id]) &&
5226 		    skl_ddb_entry_equal(&old_crtc_state->wm.skl.plane_ddb_uv[plane_id],
5227 					&new_crtc_state->wm.skl.plane_ddb_uv[plane_id]))
5234 		new_crtc_state->update_planes |= BIT(plane_id);
5293 			enum plane_id plane_id = plane->id;
5296 			old = &old_crtc_state->wm.skl.plane_ddb_y[plane_id];
5297 			new = &new_crtc_state->wm.skl.plane_ddb_y[plane_id];
5310 			enum plane_id plane_id = plane->id;
5313 			old_wm = &old_pipe_wm->planes[plane_id];
5314 			new_wm = &new_pipe_wm->planes[plane_id];
5495 		enum plane_id plane_id = plane->id;
5507 					&old_crtc_state->wm.skl.optimal.planes[plane_id],
5508 					&new_crtc_state->wm.skl.optimal.planes[plane_id]))
5515 		new_crtc_state->update_planes |= BIT(plane_id);
5697 	enum plane_id plane_id;
5702 	for_each_plane_id_on_crtc(crtc, plane_id) {
5703 		struct skl_plane_wm *wm = &out->planes[plane_id];
5706 			if (plane_id != PLANE_CURSOR)
5707 				val = I915_READ(PLANE_WM(pipe, plane_id, level));
5714 		if (plane_id != PLANE_CURSOR)
5715 			val = I915_READ(PLANE_WM_TRANS(pipe, plane_id));
5924 		enum plane_id plane_id;
5934 		for_each_plane_id_on_crtc(crtc, plane_id) {
5935 			active->wm.plane[plane_id] =
5936 				wm->pipe[pipe].plane[plane_id];
5948 		for_each_plane_id_on_crtc(crtc, plane_id)
5949 			raw->plane[plane_id] = active->wm.plane[plane_id];
5970 		for_each_plane_id_on_crtc(crtc, plane_id)
5972 					     plane_id, USHRT_MAX);
6011 		enum plane_id plane_id = plane->id;
6021 			raw->plane[plane_id] = 0;
6022 			wm_state->wm.plane[plane_id] = 0;
6025 		if (plane_id == PLANE_PRIMARY) {
6105 		enum plane_id plane_id;
6120 			for_each_plane_id_on_crtc(crtc, plane_id) {
6121 				active->wm[level].plane[plane_id] =
6122 					wm->pipe[pipe].plane[plane_id];
6124 				raw->plane[plane_id] =
6125 					vlv_invert_wm_value(active->wm[level].plane[plane_id],
6126 							    fifo_state->plane[plane_id]);
6130 		for_each_plane_id_on_crtc(crtc, plane_id)
6132 					     plane_id, USHRT_MAX);
6169 		enum plane_id plane_id = plane->id;
6179 			raw->plane[plane_id] = 0;
6181 			wm_state->wm[level].plane[plane_id] =
6182 				vlv_invert_wm_value(raw->plane[plane_id],
6183 						    fifo_state->plane[plane_id]);