drm/i915/intel_csr.c

37  * DOC: csr support for dmc
310 	u32 *payload = dev_priv->csr.dmc_payload;
318 	if (!dev_priv->csr.dmc_payload) {
323 	fw_size = dev_priv->csr.dmc_fw_size;
333 	for (i = 0; i < dev_priv->csr.mmio_count; i++) {
334 		I915_WRITE(dev_priv->csr.mmioaddr[i],
335 			   dev_priv->csr.mmiodata[i]);
338 	dev_priv->csr.dc_state = 0;
387 static u32 parse_csr_fw_dmc(struct intel_csr *csr,
396 	BUILD_BUG_ON(ARRAY_SIZE(csr->mmioaddr) < DMC_V3_MAX_MMIO_COUNT ||
397 		     ARRAY_SIZE(csr->mmioaddr) < DMC_V1_MAX_MMIO_COUNT);
459 		csr->mmioaddr[i] = _MMIO(mmioaddr[i]);
460 		csr->mmiodata[i] = mmiodata[i];
462 	csr->mmio_count = mmio_count;
471 	if (payload_size > csr->max_fw_size) {
475 	csr->dmc_fw_size = dmc_header->fw_size;
477 	csr->dmc_payload = kmalloc(payload_size, GFP_KERNEL);
478 	if (!csr->dmc_payload) {
484 	memcpy(csr->dmc_payload, payload, payload_size);
494 parse_csr_fw_package(struct intel_csr *csr,
553 static u32 parse_csr_fw_css(struct intel_csr *csr,
570 	if (csr->required_version &&
571 	    css_header->version != csr->required_version) {
576 			 CSR_VERSION_MAJOR(csr->required_version),
577 			 CSR_VERSION_MINOR(csr->required_version));
581 	csr->version = css_header->version;
592 	struct intel_csr *csr = &dev_priv->csr;
602 	r = parse_csr_fw_css(csr, css_header, fw->size);
610 	r = parse_csr_fw_package(csr, package_header, si, fw->size - readcount);
618 	parse_csr_fw_dmc(csr, dmc_header, fw->size - readcount);
623 	WARN_ON(dev_priv->csr.wakeref);
624 	dev_priv->csr.wakeref =
631 		fetch_and_zero(&dev_priv->csr.wakeref);
639 	struct intel_csr *csr;
642 	dev_priv = container_of(work, typeof(*dev_priv), csr.work);
643 	csr = &dev_priv->csr;
645 	request_firmware(&fw, dev_priv->csr.fw_path,
649 	if (dev_priv->csr.dmc_payload) {
654 			 dev_priv->csr.fw_path,
655 			 CSR_VERSION_MAJOR(csr->version),
656 			 CSR_VERSION_MINOR(csr->version));
661 			   csr->fw_path);
680 	struct intel_csr *csr = &dev_priv->csr;
682 	INIT_WORK(&dev_priv->csr.work, csr_load_work_fn);
698 		csr->fw_path = TGL_CSR_PATH;
699 		csr->required_version = TGL_CSR_VERSION_REQUIRED;
701 		csr->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
703 		csr->fw_path = ICL_CSR_PATH;
704 		csr->required_version = ICL_CSR_VERSION_REQUIRED;
705 		csr->max_fw_size = ICL_CSR_MAX_FW_SIZE;
707 		csr->fw_path = CNL_CSR_PATH;
708 		csr->required_version = CNL_CSR_VERSION_REQUIRED;
709 		csr->max_fw_size = CNL_CSR_MAX_FW_SIZE;
711 		csr->fw_path = GLK_CSR_PATH;
712 		csr->required_version = GLK_CSR_VERSION_REQUIRED;
713 		csr->max_fw_size = GLK_CSR_MAX_FW_SIZE;
715 		csr->fw_path = KBL_CSR_PATH;
716 		csr->required_version = KBL_CSR_VERSION_REQUIRED;
717 		csr->max_fw_size = KBL_CSR_MAX_FW_SIZE;
719 		csr->fw_path = SKL_CSR_PATH;
720 		csr->required_version = SKL_CSR_VERSION_REQUIRED;
721 		csr->max_fw_size = SKL_CSR_MAX_FW_SIZE;
723 		csr->fw_path = BXT_CSR_PATH;
724 		csr->required_version = BXT_CSR_VERSION_REQUIRED;
725 		csr->max_fw_size = BXT_CSR_MAX_FW_SIZE;
730 			csr->fw_path = NULL;
735 		csr->fw_path = i915_modparams.dmc_firmware_path;
737 		csr->required_version = 0;
740 	if (csr->fw_path == NULL) {
745 	DRM_DEBUG_KMS("Loading %s\n", csr->fw_path);
746 	schedule_work(&dev_priv->csr.work);
762 	flush_work(&dev_priv->csr.work);
765 	if (!dev_priv->csr.dmc_payload)
785 	if (!dev_priv->csr.dmc_payload)
802 	WARN_ON(dev_priv->csr.wakeref);
804 	kfree(dev_priv->csr.dmc_payload);