drm/i915/i915_reg.h

2079 #define MG_PHY_PORT_LN(ln, tc_port, ln0p1, ln0p2, ln1p1) \
2080 	_MMIO(_PORT(tc_port, ln0p1, ln0p2) + (ln) * ((ln1p1) - (ln0p1)))
2090 #define MG_TX1_LINK_PARAMS(ln, tc_port) \
2091 	MG_PHY_PORT_LN(ln, tc_port, MG_TX_LINK_PARAMS_TX1LN0_PORT1, \
2103 #define MG_TX2_LINK_PARAMS(ln, tc_port) \
2104 	MG_PHY_PORT_LN(ln, tc_port, MG_TX_LINK_PARAMS_TX2LN0_PORT1, \
2117 #define MG_TX1_PISO_READLOAD(ln, tc_port) \
2118 	MG_PHY_PORT_LN(ln, tc_port, MG_TX_PISO_READLOAD_TX1LN0_PORT1, \
2130 #define MG_TX2_PISO_READLOAD(ln, tc_port) \
2131 	MG_PHY_PORT_LN(ln, tc_port, MG_TX_PISO_READLOAD_TX2LN0_PORT1, \
2144 #define MG_TX1_SWINGCTRL(ln, tc_port) \
2145 	MG_PHY_PORT_LN(ln, tc_port, MG_TX_SWINGCTRL_TX1LN0_PORT1, \
2157 #define MG_TX2_SWINGCTRL(ln, tc_port) \
2158 	MG_PHY_PORT_LN(ln, tc_port, MG_TX_SWINGCTRL_TX2LN0_PORT1, \
2172 #define MG_TX1_DRVCTRL(ln, tc_port) \
2173 	MG_PHY_PORT_LN(ln, tc_port, MG_TX_DRVCTRL_TX1LN0_TXPORT1, \
2185 #define MG_TX2_DRVCTRL(ln, tc_port) \
2186 	MG_PHY_PORT_LN(ln, tc_port, MG_TX_DRVCTRL_TX2LN0_PORT1, \
2205 #define MG_CLKHUB(ln, tc_port) \
2206 	MG_PHY_PORT_LN(ln, tc_port, MG_CLKHUB_LN0_PORT1, \
2219 #define MG_TX1_DCC(ln, tc_port) \
2220 	MG_PHY_PORT_LN(ln, tc_port, MG_TX_DCC_TX1LN0_PORT1, \
2231 #define MG_TX2_DCC(ln, tc_port) \
2232 	MG_PHY_PORT_LN(ln, tc_port, MG_TX_DCC_TX2LN0_PORT1, \
2247 #define MG_DP_MODE(ln, tc_port)	\
2248 	MG_PHY_PORT_LN(ln, tc_port, MG_DP_MODE_LN0_ACU_PORT1, \
7590 #define  GEN11_TC_HOTPLUG(tc_port)		(1 << ((tc_port) + 16))
7603 #define  GEN11_TBT_HOTPLUG(tc_port)		(1 << (tc_port))
7613 #define  GEN11_HOTPLUG_CTL_ENABLE(tc_port)		(8 << (tc_port) * 4)
7614 #define  GEN11_HOTPLUG_CTL_LONG_DETECT(tc_port)		(2 << (tc_port) * 4)
7615 #define  GEN11_HOTPLUG_CTL_SHORT_DETECT(tc_port)	(1 << (tc_port) * 4)
7616 #define  GEN11_HOTPLUG_CTL_NO_DETECT(tc_port)		(0 << (tc_port) * 4)
8026 #define SDE_TC_HOTPLUG_ICP(tc_port)	(1 << ((tc_port) + 24))
8118 #define   ICP_TC_HPD_ENABLE(tc_port)		(8 << (tc_port) * 4)
8227 #define   ICP_TC_HPD_LONG_DETECT(tc_port)	(2 << (tc_port) * 4)
8228 #define   ICP_TC_HPD_SHORT_DETECT(tc_port)	(1 << (tc_port) * 4)
10033 #define  ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)	(1 << ((tc_port) < PORT_TC4 ? \
10034 						       (tc_port) + 12 : \
10035 						       (tc_port) - PORT_TC4 + 21))
10056 #define MG_PLL_ENABLE(tc_port)	_MMIO_PORT((tc_port), _MG_PLL1_ENABLE, \
10065 #define MG_REFCLKIN_CTL(tc_port) _MMIO_PORT((tc_port), \
10077 #define MG_CLKTOP2_CORECLKCTL1(tc_port) _MMIO_PORT((tc_port), \
10097 #define MG_CLKTOP2_HSCLKCTL(tc_port) _MMIO_PORT((tc_port), \
10111 #define MG_PLL_DIV0(tc_port) _MMIO_PORT((tc_port), _MG_PLL_DIV0_PORT1, \
10126 #define MG_PLL_DIV1(tc_port) _MMIO_PORT((tc_port), _MG_PLL_DIV1_PORT1, \
10139 #define MG_PLL_LF(tc_port) _MMIO_PORT((tc_port), _MG_PLL_LF_PORT1, \
10152 #define MG_PLL_FRAC_LOCK(tc_port) _MMIO_PORT((tc_port), \
10166 #define MG_PLL_SSC(tc_port) _MMIO_PORT((tc_port), _MG_PLL_SSC_PORT1, \
10186 #define MG_PLL_BIAS(tc_port) _MMIO_PORT((tc_port), _MG_PLL_BIAS_PORT1, \
10198 #define MG_PLL_TDC_COLDST_BIAS(tc_port) _MMIO_PORT((tc_port), \
10291 #define DKL_PLL_DIV0(tc_port)		_MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \
10300 #define DKL_PLL_DIV1(tc_port)		_MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \
10312 #define DKL_PLL_SSC(tc_port)		_MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \
10321 #define DKL_PLL_BIAS(tc_port)		_MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \
10330 #define DKL_PLL_TDC_COLDST_BIAS(tc_port) _MMIO(_PORT(tc_port, \
10337 #define DKL_REFCLKIN_CTL(tc_port)	_MMIO(_PORT(tc_port, \
10344 #define DKL_CLKTOP2_HSCLKCTL(tc_port)	_MMIO(_PORT(tc_port, \
10351 #define DKL_CLKTOP2_CORECLKCTL1(tc_port)	_MMIO(_PORT(tc_port, \
10363 #define DKL_TX_DPCNTL0(tc_port) _MMIO(_PORT(tc_port, \
10370 #define DKL_TX_DPCNTL1(tc_port) _MMIO(_PORT(tc_port, \
10377 #define DKL_TX_DPCNTL2(tc_port) _MMIO(_PORT(tc_port, \
10384 #define DKL_TX_FW_CALIB(tc_port) _MMIO(_PORT(tc_port, \
10390 #define DKL_TX_PMD_LANE_SUS(tc_port) _MMIO(_PORT(tc_port, \
10396 #define DKL_TX_DW17(tc_port) _MMIO(_PORT(tc_port, \
10402 #define DKL_TX_DW18(tc_port) _MMIO(_PORT(tc_port, \
10408 #define DKL_DP_MODE(tc_port) _MMIO(_PORT(tc_port, \
10415 #define DKL_CMN_UC_DW_27(tc_port)		_MMIO(_PORT(tc_port, \
10428 #define HIP_INDEX_REG(tc_port)		_MMIO((tc_port) < 4 ? _HIP_INDEX_REG0 \
10430 #define _HIP_INDEX_SHIFT(tc_port)	(8 * ((tc_port) % 4))
10431 #define HIP_INDEX_VAL(tc_port, val)	((val) << _HIP_INDEX_SHIFT(tc_port))