Lines Matching defs:value
22 int value;
32 value = i915->drm.pdev->device;
35 value = i915->drm.pdev->revision;
38 value = i915->ggtt.num_fences;
41 value = !!i915->overlay;
44 value = !!intel_engine_lookup_user(i915,
48 value = !!intel_engine_lookup_user(i915,
52 value = !!intel_engine_lookup_user(i915,
56 value = !!intel_engine_lookup_user(i915,
60 value = HAS_LLC(i915);
63 value = HAS_WT(i915);
66 value = INTEL_PPGTT(i915);
69 value = !!(i915->caps.scheduler & I915_SCHEDULER_CAP_SEMAPHORES);
72 value = HAS_SECURE_BATCHES(i915) && capable(CAP_SYS_ADMIN);
75 value = i915_cmd_parser_get_version(i915);
78 value = intel_sseu_subslice_total(sseu);
79 if (!value)
83 value = sseu->eu_total;
84 if (!value)
88 value = i915_modparams.enable_hangcheck &&
90 if (value && intel_has_reset_engine(&i915->gt))
91 value = 2;
94 value = 0;
97 value = HAS_POOLED_EU(i915);
100 value = sseu->min_eu_in_pool;
103 value = intel_huc_check_status(&i915->gt.uc.huc);
104 if (value < 0)
105 return value;
109 * earlier versions as 0, in effect their value is undefined as
112 value = i915_gem_mmap_gtt_version();
115 value = i915->caps.scheduler;
146 * features this value needs to be provided from
149 value = 1;
152 value = intel_engines_has_context_isolation(i915);
155 value = sseu->slice_mask;
156 if (!value)
160 value = sseu->subslice_mask[0];
161 if (!value)
165 value = 1000 * RUNTIME_INFO(i915)->cs_timestamp_frequency_khz;
168 value = INTEL_INFO(i915)->has_coherent_ggtt;
171 value = i915_perf_ioctl_version();
178 if (put_user(value, param->value))