i915/gt/intel_renderstate.c

11  * Software is furnished to do so, subject to the following conditions:
65  * right after the commands taking care of alignment so we should sufficient
75 static int render_state_setup(struct intel_renderstate *so,
78 	const struct intel_renderstate_rodata *rodata = so->rodata;
84 	ret = i915_gem_object_prepare_write(so->vma->obj, &needs_clflush);
88 	d = kmap_atomic(i915_gem_object_get_dirty_page(so->vma->obj, 0));
94 			u64 r = s + so->vma->node.start;
116 	so->batch_offset = i915_ggtt_offset(so->vma);
117 	so->batch_size = rodata->batch_items * sizeof(u32);
122 	so->aux_offset = i * sizeof(u32);
152 	so->aux_size = i * sizeof(u32) - so->aux_offset;
153 	so->aux_offset += so->batch_offset;
158 	so->aux_size = ALIGN(so->aux_size, 8);
166 	i915_gem_object_finish_access(so->vma->obj);
177 int intel_renderstate_init(struct intel_renderstate *so,
183 	memset(so, 0, sizeof(*so));
185 	so->rodata = render_state_get_rodata(engine);
186 	if (!so->rodata)
189 	if (so->rodata->batch_items * 4 > PAGE_SIZE)
196 	so->vma = i915_vma_instance(obj, &engine->gt->ggtt->vm, NULL);
197 	if (IS_ERR(so->vma)) {
198 		err = PTR_ERR(so->vma);
202 	err = i915_vma_pin(so->vma, 0, 0, PIN_GLOBAL | PIN_HIGH);
206 	err = render_state_setup(so, engine->i915);
213 	i915_vma_unpin(so->vma);
215 	i915_vma_close(so->vma);
218 	so->vma = NULL;
222 int intel_renderstate_emit(struct intel_renderstate *so,
228 	if (!so->vma)
232 				    so->batch_offset, so->batch_size,
237 	if (so->aux_size > 8) {
239 					    so->aux_offset, so->aux_size,
245 	i915_vma_lock(so->vma);
246 	err = i915_request_await_object(rq, so->vma->obj, false);
248 		err = i915_vma_move_to_active(so->vma, rq, 0);
249 	i915_vma_unlock(so->vma);
254 void intel_renderstate_fini(struct intel_renderstate *so)
256 	i915_vma_unpin_and_release(&so->vma, 0);