i915/display/vlv_dsi.c

81 void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum port port)
91 	if (intel_de_wait_for_set(dev_priv, MIPI_GEN_FIFO_STAT(port),
132 	enum port port = intel_dsi_host->port;
147 		data_reg = MIPI_LP_GEN_DATA(port);
149 		ctrl_reg = MIPI_LP_GEN_CTRL(port);
152 		data_reg = MIPI_HS_GEN_DATA(port);
154 		ctrl_reg = MIPI_HS_GEN_CTRL(port);
160 		if (intel_de_wait_for_clear(dev_priv, MIPI_GEN_FIFO_STAT(port),
169 		I915_WRITE(MIPI_INTR_STAT(port), GEN_READ_DATA_AVAIL);
172 	if (intel_de_wait_for_clear(dev_priv, MIPI_GEN_FIFO_STAT(port),
182 		if (intel_de_wait_for_set(dev_priv, MIPI_INTR_STAT(port),
217 			enum port port)
231 	I915_WRITE(MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT);
234 	if (cmd == I915_READ(MIPI_DPI_CONTROL(port)))
237 	I915_WRITE(MIPI_DPI_CONTROL(port), cmd);
240 	if (intel_de_wait_for_set(dev_priv, MIPI_INTR_STAT(port), mask, 100))
327 	enum port port;
335 	for_each_dsi_port(port, intel_dsi->ports) {
336 		tmp = I915_READ(MIPI_CTRL(port));
337 		I915_WRITE(MIPI_CTRL(port), tmp | GLK_MIPIIO_ENABLE);
346 	for_each_dsi_port(port, intel_dsi->ports) {
347 		tmp = I915_READ(MIPI_CTRL(port));
348 		if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY))
352 		I915_WRITE(MIPI_CTRL(port), tmp);
356 	for_each_dsi_port(port, intel_dsi->ports) {
357 		if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port),
359 			DRM_ERROR("MIPIO port is powergated\n");
363 	for_each_dsi_port(port, intel_dsi->ports) {
365 			!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY);
375 	enum port port;
379 	for_each_dsi_port(port, intel_dsi->ports) {
380 		if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port),
390 	for_each_dsi_port(port, intel_dsi->ports) {
391 		if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY)) {
392 			val = I915_READ(MIPI_DEVICE_READY(port));
395 			I915_WRITE(MIPI_DEVICE_READY(port), val);
399 			val = I915_READ(MIPI_DEVICE_READY(port));
402 			I915_WRITE(MIPI_DEVICE_READY(port), val);
405 			if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port),
410 			val = I915_READ(MIPI_DEVICE_READY(port));
413 			I915_WRITE(MIPI_DEVICE_READY(port), val);
416 			val = I915_READ(MIPI_DEVICE_READY(port));
419 			I915_WRITE(MIPI_DEVICE_READY(port), val);
421 			val = I915_READ(MIPI_CTRL(port));
423 			I915_WRITE(MIPI_CTRL(port), val);
428 	for_each_dsi_port(port, intel_dsi->ports) {
429 		if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port),
435 	for_each_dsi_port(port, intel_dsi->ports) {
436 		if (intel_de_wait_for_set(dev_priv, BXT_MIPI_PORT_CTRL(port),
446 	enum port port;
452 	for_each_dsi_port(port, intel_dsi->ports) {
453 		val = I915_READ(BXT_MIPI_PORT_CTRL(port));
454 		I915_WRITE(BXT_MIPI_PORT_CTRL(port), val | LP_OUTPUT_HOLD);
459 	for_each_dsi_port(port, intel_dsi->ports) {
460 		val = I915_READ(MIPI_DEVICE_READY(port));
462 		I915_WRITE(MIPI_DEVICE_READY(port), val);
465 		I915_WRITE(MIPI_DEVICE_READY(port), val);
473 	enum port port;
487 	for_each_dsi_port(port, intel_dsi->ports) {
489 		I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_ENTER);
500 		I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_EXIT);
503 		I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY);
524 	enum port port;
528 	for_each_dsi_port(port, intel_dsi->ports) {
529 		val = I915_READ(MIPI_DEVICE_READY(port));
532 		I915_WRITE(MIPI_DEVICE_READY(port), val);
536 	for_each_dsi_port(port, intel_dsi->ports) {
537 		if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port),
543 	for_each_dsi_port(port, intel_dsi->ports) {
544 		if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port),
554 	enum port port;
563 	for_each_dsi_port(port, intel_dsi->ports) {
564 		if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port),
570 	for_each_dsi_port(port, intel_dsi->ports) {
571 		tmp = I915_READ(MIPI_CTRL(port));
573 		I915_WRITE(MIPI_CTRL(port), tmp);
587 	enum port port;
590 	for_each_dsi_port(port, intel_dsi->ports) {
593 			BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(PORT_A);
596 		I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
600 		I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
604 		I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
612 		if ((IS_GEN9_LP(dev_priv) || port == PORT_A) &&
622 		I915_WRITE(MIPI_DEVICE_READY(port), 0x00);
633 	enum port port;
638 			for_each_dsi_port(port, intel_dsi->ports) {
639 				temp = I915_READ(MIPI_CTRL(port));
643 				I915_WRITE(MIPI_CTRL(port), temp);
654 	for_each_dsi_port(port, intel_dsi->ports) {
656 			BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
689 	enum port port;
691 	for_each_dsi_port(port, intel_dsi->ports) {
693 			BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
745  * DSI port enable has to be done before pipe and plane enable, so we do it in
757 	enum port port;
809 		/* Prepare port in cold boot(s3/s4) scenario */
817 	/* Prepare port in normal boot scenario */
824 	/* Enable port in pre-enable phase itself because as per hw team
825 	 * recommendation, port should be enabled befor plane & pipe */
827 		for_each_dsi_port(port, intel_dsi->ports)
828 			I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4);
833 		for_each_dsi_port(port, intel_dsi->ports)
834 			dpi_send_cmd(intel_dsi, TURN_ON, false, port);
847  * DSI port disable has to be done after pipe and plane disable, so we do it in
855 	enum port port;
869 		for_each_dsi_port(port, intel_dsi->ports)
870 			dpi_send_cmd(intel_dsi, SHUTDOWN, false, port);
891 	enum port port;
903 		for_each_dsi_port(port, intel_dsi->ports)
904 			vlv_dsi_wait_for_fifo_empty(intel_dsi, port);
965 	enum port port;
984 	for_each_dsi_port(port, intel_dsi->ports) {
986 			BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
991 		 * bit in port C control register does not get set. As a
995 		    port == PORT_C)
1000 			u32 tmp = I915_READ(MIPI_DSI_FUNC_PRG(port));
1007 		if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY))
1011 			u32 tmp = I915_READ(MIPI_CTRL(port));
1020 			*pipe = port == PORT_A ? PIPE_A : PIPE_B;
1045 	enum port port;
1055 	 * Atleast one port is active as encoder->get_config called only if
1058 	for_each_dsi_port(port, intel_dsi->ports) {
1059 		if (I915_READ(BXT_MIPI_PORT_CTRL(port)) & DPI_ENABLE)
1063 	fmt = I915_READ(MIPI_DSI_FUNC_PRG(port)) & VID_MODE_FORMAT_MASK;
1075 				I915_READ(BXT_MIPI_TRANS_HACTIVE(port));
1077 				I915_READ(BXT_MIPI_TRANS_VACTIVE(port));
1079 				I915_READ(BXT_MIPI_TRANS_VTOTAL(port));
1082 	hfp = I915_READ(MIPI_HFP_COUNT(port));
1088 	hsync = I915_READ(MIPI_HSYNC_PADDING_COUNT(port));
1089 	hbp = I915_READ(MIPI_HBP_COUNT(port));
1106 	vfp = I915_READ(MIPI_VFP_COUNT(port));
1107 	vsync = I915_READ(MIPI_VSYNC_PADDING_COUNT(port));
1108 	vbp = I915_READ(MIPI_VBP_COUNT(port));
1126 	 * value programmed to the port and then back to the horizontal timing
1128 	 * And if that is same as retrieved value from port, then
1153 	/* Reverse calculating the adjusted mode parameters from port reg vals*/
1236 	enum port port;
1268 	for_each_dsi_port(port, intel_dsi->ports) {
1276 			I915_WRITE(BXT_MIPI_TRANS_HACTIVE(port),
1278 			I915_WRITE(BXT_MIPI_TRANS_VACTIVE(port),
1280 			I915_WRITE(BXT_MIPI_TRANS_VTOTAL(port),
1284 		I915_WRITE(MIPI_HACTIVE_AREA_COUNT(port), hactive);
1285 		I915_WRITE(MIPI_HFP_COUNT(port), hfp);
1289 		I915_WRITE(MIPI_HSYNC_PADDING_COUNT(port), hsync);
1290 		I915_WRITE(MIPI_HBP_COUNT(port), hbp);
1293 		I915_WRITE(MIPI_VFP_COUNT(port), vfp);
1294 		I915_WRITE(MIPI_VSYNC_PADDING_COUNT(port), vsync);
1295 		I915_WRITE(MIPI_VBP_COUNT(port), vbp);
1325 	enum port port;
1340 	for_each_dsi_port(port, intel_dsi->ports) {
1352 			tmp = I915_READ(MIPI_CTRL(port));
1354 			I915_WRITE(MIPI_CTRL(port), tmp |
1359 			tmp = I915_READ(MIPI_CTRL(port));
1363 			I915_WRITE(MIPI_CTRL(port), tmp);
1367 		I915_WRITE(MIPI_INTR_STAT(port), 0xffffffff);
1368 		I915_WRITE(MIPI_INTR_EN(port), 0xffffffff);
1370 		I915_WRITE(MIPI_DPHY_PARAM(port), intel_dsi->dphy_reg);
1372 		I915_WRITE(MIPI_DPI_RESOLUTION(port),
1400 	for_each_dsi_port(port, intel_dsi->ports) {
1401 		I915_WRITE(MIPI_DSI_FUNC_PRG(port), val);
1422 			I915_WRITE(MIPI_HS_TX_TIMEOUT(port),
1427 			I915_WRITE(MIPI_HS_TX_TIMEOUT(port),
1433 		I915_WRITE(MIPI_LP_RX_TIMEOUT(port), intel_dsi->lp_rx_timeout);
1434 		I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(port),
1436 		I915_WRITE(MIPI_DEVICE_RESET_TIMER(port),
1442 		I915_WRITE(MIPI_INIT_COUNT(port),
1449 			 * getting used. So write the other port
1452 			I915_WRITE(MIPI_INIT_COUNT(port ==
1458 		I915_WRITE(MIPI_EOT_DISABLE(port), tmp);
1461 		I915_WRITE(MIPI_INIT_COUNT(port), intel_dsi->init_count);
1468 		I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(port),
1477 		I915_WRITE(MIPI_LP_BYTECLK(port), intel_dsi->lp_byte_clk);
1480 			I915_WRITE(MIPI_TLPX_TIME_COUNT(port),
1483 			I915_WRITE(MIPI_CLK_LANE_TIMING(port),
1492 		I915_WRITE(MIPI_DBI_BW_CTRL(port), intel_dsi->bw_timer);
1494 		I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(port),
1502 			I915_WRITE(MIPI_VIDEO_MODE_FORMAT(port),
1514 	enum port port;
1520 	for_each_dsi_port(port, intel_dsi->ports) {
1522 		I915_WRITE(MIPI_DEVICE_READY(port), 0x0);
1525 			bxt_dsi_reset_clocks(encoder, port);
1527 			vlv_dsi_reset_clocks(encoder, port);
1528 		I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
1530 		val = I915_READ(MIPI_DSI_FUNC_PRG(port));
1532 		I915_WRITE(MIPI_DSI_FUNC_PRG(port), val);
1534 		I915_WRITE(MIPI_DEVICE_READY(port), 0x1);
1822 	enum port port;
1828 	if (!intel_bios_is_dsi_present(dev_priv, &port))
1853 			 "DSI %c", port_name(port));
1865 	intel_encoder->port = port;
1871 	 * On BYT/CHV, pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI
1872 	 * port C. BXT isn't limited like this.
1876 	else if (port == PORT_A)
1884 		intel_dsi->ports = BIT(port);
1889 	/* Create a DSI host (and a device) for each port. */
1890 	for_each_dsi_port(port, intel_dsi->ports) {
1894 					   port);
1898 		intel_dsi->dsi_hosts[port] = host;