Lines Matching defs:tc_port
2661 static enum tc_port icl_pll_id_to_tc_port(enum intel_dpll_id id)
2666 enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port)
2668 return tc_port + DPLL_ID_ICL_MGPLL1;
3140 enum tc_port tc_port = icl_pll_id_to_tc_port(id);
3150 val = I915_READ(MG_PLL_ENABLE(tc_port));
3154 hw_state->mg_refclkin_ctl = I915_READ(MG_REFCLKIN_CTL(tc_port));
3158 I915_READ(MG_CLKTOP2_CORECLKCTL1(tc_port));
3163 I915_READ(MG_CLKTOP2_HSCLKCTL(tc_port));
3170 hw_state->mg_pll_div0 = I915_READ(MG_PLL_DIV0(tc_port));
3171 hw_state->mg_pll_div1 = I915_READ(MG_PLL_DIV1(tc_port));
3172 hw_state->mg_pll_lf = I915_READ(MG_PLL_LF(tc_port));
3173 hw_state->mg_pll_frac_lock = I915_READ(MG_PLL_FRAC_LOCK(tc_port));
3174 hw_state->mg_pll_ssc = I915_READ(MG_PLL_SSC(tc_port));
3176 hw_state->mg_pll_bias = I915_READ(MG_PLL_BIAS(tc_port));
3178 I915_READ(MG_PLL_TDC_COLDST_BIAS(tc_port));
3202 enum tc_port tc_port = icl_pll_id_to_tc_port(id);
3212 val = I915_READ(MG_PLL_ENABLE(tc_port));
3220 I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, 0x2));
3222 hw_state->mg_refclkin_ctl = I915_READ(DKL_REFCLKIN_CTL(tc_port));
3226 I915_READ(DKL_CLKTOP2_HSCLKCTL(tc_port));
3234 I915_READ(DKL_CLKTOP2_CORECLKCTL1(tc_port));
3238 hw_state->mg_pll_div0 = I915_READ(DKL_PLL_DIV0(tc_port));
3244 hw_state->mg_pll_div1 = I915_READ(DKL_PLL_DIV1(tc_port));
3248 hw_state->mg_pll_ssc = I915_READ(DKL_PLL_SSC(tc_port));
3254 hw_state->mg_pll_bias = I915_READ(DKL_PLL_BIAS(tc_port));
3259 I915_READ(DKL_PLL_TDC_COLDST_BIAS(tc_port));
3357 enum tc_port tc_port = icl_pll_id_to_tc_port(pll->info->id);
3366 val = I915_READ(MG_REFCLKIN_CTL(tc_port));
3369 I915_WRITE(MG_REFCLKIN_CTL(tc_port), val);
3371 val = I915_READ(MG_CLKTOP2_CORECLKCTL1(tc_port));
3374 I915_WRITE(MG_CLKTOP2_CORECLKCTL1(tc_port), val);
3376 val = I915_READ(MG_CLKTOP2_HSCLKCTL(tc_port));
3382 I915_WRITE(MG_CLKTOP2_HSCLKCTL(tc_port), val);
3384 I915_WRITE(MG_PLL_DIV0(tc_port), hw_state->mg_pll_div0);
3385 I915_WRITE(MG_PLL_DIV1(tc_port), hw_state->mg_pll_div1);
3386 I915_WRITE(MG_PLL_LF(tc_port), hw_state->mg_pll_lf);
3387 I915_WRITE(MG_PLL_FRAC_LOCK(tc_port), hw_state->mg_pll_frac_lock);
3388 I915_WRITE(MG_PLL_SSC(tc_port), hw_state->mg_pll_ssc);
3390 val = I915_READ(MG_PLL_BIAS(tc_port));
3393 I915_WRITE(MG_PLL_BIAS(tc_port), val);
3395 val = I915_READ(MG_PLL_TDC_COLDST_BIAS(tc_port));
3398 I915_WRITE(MG_PLL_TDC_COLDST_BIAS(tc_port), val);
3400 POSTING_READ(MG_PLL_TDC_COLDST_BIAS(tc_port));
3407 enum tc_port tc_port = icl_pll_id_to_tc_port(pll->info->id);
3414 I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, 0x2));
3417 val = I915_READ(DKL_REFCLKIN_CTL(tc_port));
3420 I915_WRITE(DKL_REFCLKIN_CTL(tc_port), val);
3422 val = I915_READ(DKL_CLKTOP2_CORECLKCTL1(tc_port));
3425 I915_WRITE(DKL_CLKTOP2_CORECLKCTL1(tc_port), val);
3427 val = I915_READ(DKL_CLKTOP2_HSCLKCTL(tc_port));
3433 I915_WRITE(DKL_CLKTOP2_HSCLKCTL(tc_port), val);
3435 val = I915_READ(DKL_PLL_DIV0(tc_port));
3441 I915_WRITE(DKL_PLL_DIV0(tc_port), val);
3443 val = I915_READ(DKL_PLL_DIV1(tc_port));
3447 I915_WRITE(DKL_PLL_DIV1(tc_port), val);
3449 val = I915_READ(DKL_PLL_SSC(tc_port));
3455 I915_WRITE(DKL_PLL_SSC(tc_port), val);
3457 val = I915_READ(DKL_PLL_BIAS(tc_port));
3461 I915_WRITE(DKL_PLL_BIAS(tc_port), val);
3463 val = I915_READ(DKL_PLL_TDC_COLDST_BIAS(tc_port));
3467 I915_WRITE(DKL_PLL_TDC_COLDST_BIAS(tc_port), val);
3469 POSTING_READ(DKL_PLL_TDC_COLDST_BIAS(tc_port));