i915/display/intel_dp_mst.c

41 #include "intel_dp.h"
52 	struct intel_dp *intel_dp = &intel_mst->primary->dp;
58 	bool constant_n = drm_dp_has_quirk(&intel_dp->desc,
72 		slots = drm_dp_atomic_find_vcpi_slots(state, &intel_dp->mst_mgr,
102 				  struct intel_dp *mst_port)
148 	struct intel_dp *intel_dp = &intel_mst->primary->dp;
167 			drm_dp_mst_port_has_audio(&intel_dp->mst_mgr, port);
177 	limits.max_clock = intel_dp_max_link_rate(intel_dp);
180 	limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
193 	intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits);
209 	pipe_config->mst_master_transcoder = intel_dp_mst_master_trans_compute(state, intel_dp);
327 	struct intel_dp *intel_dp = &intel_dig_port->dp;
332 	DRM_DEBUG_KMS("active links %d\n", intel_dp->active_mst_links);
334 	drm_dp_mst_reset_vcpi_slots(&intel_dp->mst_mgr, connector->port);
336 	ret = drm_dp_update_payload_part1(&intel_dp->mst_mgr);
351 	struct intel_dp *intel_dp = &intel_dig_port->dp;
358 	intel_dp->active_mst_links--;
359 	last_mst_stream = intel_dp->active_mst_links == 0;
367 	drm_dp_update_payload_part2(&intel_dp->mst_mgr);
373 	if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status,
376 	drm_dp_check_act_status(&intel_dp->mst_mgr);
378 	drm_dp_mst_deallocate_vcpi(&intel_dp->mst_mgr, connector->port);
391 	drm_dp_send_power_updown_phy(&intel_dp->mst_mgr, connector->port,
409 	DRM_DEBUG_KMS("active links %d\n", intel_dp->active_mst_links);
418 	struct intel_dp *intel_dp = &intel_dig_port->dp;
420 	if (intel_dp->active_mst_links == 0)
431 	struct intel_dp *intel_dp = &intel_dig_port->dp;
444 	first_mst_stream = intel_dp->active_mst_links == 0;
448 	DRM_DEBUG_KMS("active links %d\n", intel_dp->active_mst_links);
451 		intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
453 	drm_dp_send_power_updown_phy(&intel_dp->mst_mgr, connector->port, true);
459 	ret = drm_dp_mst_allocate_vcpi(&intel_dp->mst_mgr,
466 	intel_dp->active_mst_links++;
467 	temp = I915_READ(intel_dp->regs.dp_tp_status);
468 	I915_WRITE(intel_dp->regs.dp_tp_status, temp);
470 	ret = drm_dp_update_payload_part1(&intel_dp->mst_mgr);
491 	struct intel_dp *intel_dp = &intel_dig_port->dp;
494 	DRM_DEBUG_KMS("active links %d\n", intel_dp->active_mst_links);
496 	if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status,
500 	drm_dp_check_act_status(&intel_dp->mst_mgr);
502 	drm_dp_update_payload_part2(&intel_dp->mst_mgr);
529 	struct intel_dp *intel_dp = intel_connector->mst_port;
536 	edid = drm_dp_mst_get_edid(connector, &intel_dp->mst_mgr, intel_connector->port);
565 	struct intel_dp *intel_dp = intel_connector->mst_port;
575 	max_link_clock = intel_dp_max_link_rate(intel_dp);
576 	max_lanes = intel_dp_max_lane_count(intel_dp);
598 	struct intel_dp *intel_dp = intel_connector->mst_port;
601 	return &intel_dp->mst_encoders[crtc->pipe]->base.base;
609 	struct intel_dp *intel_dp = intel_connector->mst_port;
614 	return drm_dp_mst_detect_port(connector, ctx, &intel_dp->mst_mgr,
651 	struct intel_dp *intel_dp = container_of(mgr, struct intel_dp, mst_mgr);
652 	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
665 	intel_connector->mst_port = intel_dp;
681 			&intel_dp->mst_encoders[pipe]->base.base;
703 		intel_dp->attached_connector->base.max_bpc_property;
795 	struct intel_dp *intel_dp = &intel_dig_port->dp;
800 		intel_dp->mst_encoders[pipe] = intel_dp_create_fake_mst_encoder(intel_dig_port, pipe);
814 	struct intel_dp *intel_dp = &intel_dig_port->dp;
818 	if (!HAS_DP_MST(i915) || intel_dp_is_edp(intel_dp))
827 	intel_dp->mst_mgr.cbs = &mst_cbs;
831 	ret = drm_dp_mst_topology_mgr_init(&intel_dp->mst_mgr, &i915->drm,
832 					   &intel_dp->aux, 16, 3, conn_base_id);
836 	intel_dp->can_mst = true;
844 	struct intel_dp *intel_dp = &intel_dig_port->dp;
846 	if (!intel_dp->can_mst)
849 	drm_dp_mst_topology_mgr_destroy(&intel_dp->mst_mgr);