i915/display/intel_dp_link_training.c

30 #include "intel_dp.h"
43 intel_get_adjust_train(struct intel_dp *intel_dp,
52 	for (lane = 0; lane < intel_dp->lane_count; lane++) {
62 	voltage_max = intel_dp_voltage_max(intel_dp);
66 	preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
71 		intel_dp->train_set[lane] = v | p;
75 intel_dp_set_link_train(struct intel_dp *intel_dp,
78 	u8 buf[sizeof(intel_dp->train_set) + 1];
81 	intel_dp_program_link_training_pattern(intel_dp, dp_train_pat);
90 		memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
91 		len = intel_dp->lane_count + 1;
94 	ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
101 intel_dp_reset_link_train(struct intel_dp *intel_dp,
104 	memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
105 	intel_dp_set_signal_levels(intel_dp);
106 	return intel_dp_set_link_train(intel_dp, dp_train_pat);
110 intel_dp_update_link_train(struct intel_dp *intel_dp)
114 	intel_dp_set_signal_levels(intel_dp);
116 	ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
117 				intel_dp->train_set, intel_dp->lane_count);
119 	return ret == intel_dp->lane_count;
122 static bool intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp)
126 	for (lane = 0; lane < intel_dp->lane_count; lane++)
127 		if ((intel_dp->train_set[lane] &
136 intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
144 	if (intel_dp->prepare_link_retrain)
145 		intel_dp->prepare_link_retrain(intel_dp);
147 	intel_dp_compute_rate(intel_dp, intel_dp->link_rate,
157 	link_config[1] = intel_dp->lane_count;
158 	if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
160 	drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
164 		drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
169 	drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
171 	intel_dp->DP |= DP_PORT_EN;
174 	if (!intel_dp_reset_link_train(intel_dp,
189 	if (intel_dp->dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14)
198 		drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
200 		if (!intel_dp_get_link_status(intel_dp, link_status)) {
205 		if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
220 		voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
223 		intel_get_adjust_train(intel_dp, link_status);
224 		if (!intel_dp_update_link_train(intel_dp)) {
229 		if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) ==
235 		if (intel_dp_link_max_vswing_reached(intel_dp))
248 static u32 intel_dp_training_pattern(struct intel_dp *intel_dp)
258 	source_tps4 = intel_dp_source_supports_hbr3(intel_dp);
259 	sink_tps4 = drm_dp_tps4_supported(intel_dp->dpcd);
262 	} else if (intel_dp->link_rate == 810000) {
273 	source_tps3 = intel_dp_source_supports_hbr2(intel_dp);
274 	sink_tps3 = drm_dp_tps3_supported(intel_dp->dpcd);
277 	} else if (intel_dp->link_rate >= 540000) {
288 intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp)
295 	training_pattern = intel_dp_training_pattern(intel_dp);
301 	if (!intel_dp_set_link_train(intel_dp,
309 		drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
310 		if (!intel_dp_get_link_status(intel_dp, link_status)) {
317 					      intel_dp->lane_count)) {
325 					 intel_dp->lane_count)) {
333 		intel_get_adjust_train(intel_dp, link_status);
334 		if (!intel_dp_update_link_train(intel_dp)) {
346 	intel_dp_set_idle_link_train(intel_dp);
352 void intel_dp_stop_link_train(struct intel_dp *intel_dp)
354 	intel_dp->link_trained = true;
356 	intel_dp_set_link_train(intel_dp,
361 intel_dp_start_link_train(struct intel_dp *intel_dp)
363 	struct intel_connector *intel_connector = intel_dp->attached_connector;
365 	if (!intel_dp_link_training_clock_recovery(intel_dp))
367 	if (!intel_dp_link_training_channel_equalization(intel_dp))
373 		      intel_dp->link_rate, intel_dp->lane_count);
380 		      intel_dp->link_rate, intel_dp->lane_count);
381 	if (!intel_dp_get_link_train_fallback_values(intel_dp,
382 						     intel_dp->link_rate,
383 						     intel_dp->lane_count))