i915/display/intel_ddi.c

41 #include "intel_dp.h"
1246 	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1250 	intel_dp->DP = intel_dig_port->saved_port_bits |
1252 	intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
2373 	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2381 						intel_dp->link_rate, &n_entries);
2387 						intel_dp->link_rate, &n_entries);
2512 		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2514 		width = intel_dp->lane_count;
2515 		rate = intel_dp->link_rate;
2638 		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2640 		width = intel_dp->lane_count;
2641 		rate = intel_dp->link_rate;
2904 static u32 intel_ddi_dp_level(struct intel_dp *intel_dp)
2906 	u8 train_set = intel_dp->train_set[0];
2913 u32 bxt_signal_levels(struct intel_dp *intel_dp)
2915 	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2918 	int level = intel_ddi_dp_level(intel_dp);
2921 		tgl_ddi_vswing_sequence(encoder, intel_dp->link_rate,
2924 		icl_ddi_vswing_sequence(encoder, intel_dp->link_rate,
2934 u32 ddi_signal_levels(struct intel_dp *intel_dp)
2936 	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2939 	int level = intel_ddi_dp_level(intel_dp);
3261 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp,
3267 	if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, DP_FEC_READY) <= 0)
3275 	struct intel_dp *intel_dp;
3281 	intel_dp = enc_to_intel_dp(encoder);
3282 	val = I915_READ(intel_dp->regs.dp_tp_ctl);
3284 	I915_WRITE(intel_dp->regs.dp_tp_ctl, val);
3286 	if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status,
3295 	struct intel_dp *intel_dp;
3301 	intel_dp = enc_to_intel_dp(encoder);
3302 	val = I915_READ(intel_dp->regs.dp_tp_ctl);
3304 	I915_WRITE(intel_dp->regs.dp_tp_ctl, val);
3305 	POSTING_READ(intel_dp->regs.dp_tp_ctl);
3392 	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3397 	int level = intel_ddi_dp_level(intel_dp);
3401 	intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
3404 	intel_dp->regs.dp_tp_ctl = TGL_DP_TP_CTL(transcoder);
3405 	intel_dp->regs.dp_tp_status = TGL_DP_TP_STATUS(transcoder);
3415 	intel_edp_panel_on(intel_dp);
3501 		intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
3503 	intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true);
3509 	intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
3518 	intel_dp_start_link_train(intel_dp);
3522 		intel_dp_stop_link_train(intel_dp);
3533 	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3539 	int level = intel_ddi_dp_level(intel_dp);
3546 	intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
3549 	intel_dp->regs.dp_tp_ctl = DP_TP_CTL(port);
3550 	intel_dp->regs.dp_tp_status = DP_TP_STATUS(port);
3552 	intel_edp_panel_on(intel_dp);
3584 		intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
3585 	intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
3587 	intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
3588 	intel_dp_start_link_train(intel_dp);
3591 		intel_dp_stop_link_train(intel_dp);
3722 		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3724 		val = I915_READ(intel_dp->regs.dp_tp_ctl);
3727 		I915_WRITE(intel_dp->regs.dp_tp_ctl, val);
3743 	struct intel_dp *intel_dp = &dig_port->dp;
3752 	intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
3778 	intel_edp_panel_vdd_on(intel_dp);
3779 	intel_edp_panel_off(intel_dp);
3924 	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3928 		intel_dp_stop_link_train(intel_dp);
3931 	intel_psr_enable(intel_dp, crtc_state);
3932 	intel_dp_vsc_enable(intel_dp, crtc_state, conn_state);
3933 	intel_dp_hdr_metadata_enable(intel_dp, crtc_state, conn_state);
3934 	intel_edp_drrs_enable(intel_dp, crtc_state);
4042 	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4044 	intel_dp->link_trained = false;
4050 	intel_edp_drrs_disable(intel_dp, old_crtc_state);
4051 	intel_psr_disable(intel_dp, old_crtc_state);
4054 	intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state,
4090 	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4094 	intel_psr_update(intel_dp, crtc_state);
4095 	intel_edp_drrs_enable(intel_dp, crtc_state);
4196 static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
4198 	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4205 	dp_tp_ctl = I915_READ(intel_dp->regs.dp_tp_ctl);
4217 		I915_WRITE(intel_dp->regs.dp_tp_ctl, dp_tp_ctl);
4218 		POSTING_READ(intel_dp->regs.dp_tp_ctl);
4226 	if (intel_dp->link_mst)
4230 		if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
4233 	I915_WRITE(intel_dp->regs.dp_tp_ctl, dp_tp_ctl);
4234 	POSTING_READ(intel_dp->regs.dp_tp_ctl);
4236 	intel_dp->DP |= DDI_BUF_CTL_ENABLE;
4237 	I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);