i915/display/intel_ddi.c

1526 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
1530 	if (pipe_config->has_pch_encoder)
1531 		dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1532 						    &pipe_config->fdi_m_n);
1533 	else if (intel_crtc_has_dp_encoder(pipe_config))
1534 		dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1535 						    &pipe_config->dp_m_n);
1536 	else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24)
1537 		dotclock = pipe_config->port_clock * 24 / pipe_config->pipe_bpp;
1539 		dotclock = pipe_config->port_clock;
1541 	if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
1542 	    !intel_crtc_has_dp_encoder(pipe_config))
1545 	if (pipe_config->pixel_multiplier)
1546 		dotclock /= pipe_config->pixel_multiplier;
1548 	pipe_config->hw.adjusted_mode.crtc_clock = dotclock;
1552 			      struct intel_crtc_state *pipe_config)
1555 	struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state;
1564 						pipe_config->shared_dpll);
1572 	pipe_config->port_clock = link_clock;
1574 	ddi_dotclock_get(pipe_config);
1578 			      struct intel_crtc_state *pipe_config)
1581 	struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state;
1621 	pipe_config->port_clock = link_clock;
1623 	ddi_dotclock_get(pipe_config);
1627 			      struct intel_crtc_state *pipe_config)
1629 	struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state;
1668 	pipe_config->port_clock = link_clock;
1670 	ddi_dotclock_get(pipe_config);
1674 			      struct intel_crtc_state *pipe_config)
1680 	val = hsw_pll_to_ddi_pll_sel(pipe_config->shared_dpll);
1715 	pipe_config->port_clock = link_clock * 2;
1717 	ddi_dotclock_get(pipe_config);
1736 			      struct intel_crtc_state *pipe_config)
1738 	pipe_config->port_clock =
1739 		bxt_calc_pll_link(&pipe_config->dpll_hw_state);
1741 	ddi_dotclock_get(pipe_config);
1745 				struct intel_crtc_state *pipe_config)
1750 		icl_ddi_clock_get(encoder, pipe_config);
1752 		cnl_ddi_clock_get(encoder, pipe_config);
1754 		bxt_ddi_clock_get(encoder, pipe_config);
1756 		skl_ddi_clock_get(encoder, pipe_config);
1758 		hsw_ddi_clock_get(encoder, pipe_config);
4268 			  struct intel_crtc_state *pipe_config)
4271 	struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
4272 	enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4279 	intel_dsc_get_config(encoder, pipe_config);
4291 	pipe_config->hw.adjusted_mode.flags |= flags;
4295 		pipe_config->pipe_bpp = 18;
4298 		pipe_config->pipe_bpp = 24;
4301 		pipe_config->pipe_bpp = 30;
4304 		pipe_config->pipe_bpp = 36;
4312 		pipe_config->has_hdmi_sink = true;
4314 		pipe_config->infoframes.enable |=
4315 			intel_hdmi_infoframes_enabled(encoder, pipe_config);
4317 		if (pipe_config->infoframes.enable)
4318 			pipe_config->has_infoframe = true;
4321 			pipe_config->hdmi_scrambling = true;
4323 			pipe_config->hdmi_high_tmds_clock_ratio = true;
4326 		pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
4327 		pipe_config->lane_count = 4;
4330 		pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
4334 			pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
4336 			pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
4337 		pipe_config->lane_count =
4339 		intel_dp_get_m_n(intel_crtc, pipe_config);
4347 				dp_tp_ctl = TGL_DP_TP_CTL(pipe_config->cpu_transcoder);
4349 			pipe_config->fec_enable =
4354 				      pipe_config->fec_enable);
4359 		pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST);
4360 		pipe_config->lane_count =
4364 			pipe_config->mst_master_transcoder =
4367 		intel_dp_get_m_n(intel_crtc, pipe_config);
4374 		tgl_dc3co_exitline_get_config(pipe_config);
4376 	pipe_config->has_audio =
4380 	    pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
4395 			      pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
4396 		dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
4399 	intel_ddi_clock_get(encoder, pipe_config);
4402 		pipe_config->lane_lat_optim_mask =
4405 	intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
4407 	intel_hdmi_read_gcp_infoframe(encoder, pipe_config);
4409 	intel_read_infoframe(encoder, pipe_config,
4411 			     &pipe_config->infoframes.avi);
4412 	intel_read_infoframe(encoder, pipe_config,
4414 			     &pipe_config->infoframes.spd);
4415 	intel_read_infoframe(encoder, pipe_config,
4417 			     &pipe_config->infoframes.hdmi);
4418 	intel_read_infoframe(encoder, pipe_config,
4420 			     &pipe_config->infoframes.drm);
4442 				    struct intel_crtc_state *pipe_config,
4445 	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
4451 		pipe_config->cpu_transcoder = TRANSCODER_EDP;
4453 	if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) {
4454 		ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state);
4456 		ret = intel_dp_compute_config(encoder, pipe_config, conn_state);
4457 		tgl_dc3co_exitline_compute_config(encoder, pipe_config);
4464 	    pipe_config->cpu_transcoder == TRANSCODER_EDP)
4465 		pipe_config->pch_pfit.force_thru =
4466 			pipe_config->pch_pfit.enabled ||
4467 			pipe_config->crc_enabled;
4470 		pipe_config->lane_lat_optim_mask =
4471 			bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
4473 	intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);