Lines Matching defs:cdclk
65 cdclk_state->cdclk = 133333;
71 cdclk_state->cdclk = 200000;
77 cdclk_state->cdclk = 266667;
83 cdclk_state->cdclk = 333333;
89 cdclk_state->cdclk = 400000;
95 cdclk_state->cdclk = 450000;
110 cdclk_state->cdclk = 133333;
124 cdclk_state->cdclk = 200000;
127 cdclk_state->cdclk = 250000;
130 cdclk_state->cdclk = 133333;
135 cdclk_state->cdclk = 266667;
149 cdclk_state->cdclk = 133333;
155 cdclk_state->cdclk = 333333;
159 cdclk_state->cdclk = 190000;
173 cdclk_state->cdclk = 133333;
179 cdclk_state->cdclk = 320000;
183 cdclk_state->cdclk = 200000;
295 cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco,
302 cdclk_state->cdclk = 190476;
315 cdclk_state->cdclk = 266667;
318 cdclk_state->cdclk = 333333;
321 cdclk_state->cdclk = 444444;
324 cdclk_state->cdclk = 200000;
330 cdclk_state->cdclk = 133333;
333 cdclk_state->cdclk = 166667;
372 cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco,
379 cdclk_state->cdclk = 200000;
399 cdclk_state->cdclk = cdclk_sel ? 333333 : 222222;
402 cdclk_state->cdclk = cdclk_sel ? 320000 : 228571;
407 cdclk_state->cdclk = 222222;
419 cdclk_state->cdclk = 800000;
421 cdclk_state->cdclk = 450000;
423 cdclk_state->cdclk = 450000;
425 cdclk_state->cdclk = 337500;
427 cdclk_state->cdclk = 540000;
450 static u8 vlv_calc_voltage_level(struct drm_i915_private *dev_priv, int cdclk)
453 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
455 else if (cdclk >= 266667)
465 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
478 cdclk_state->cdclk = vlv_get_cck_clock(dev_priv, "cdclk",
504 if (dev_priv->cdclk.hw.cdclk >= dev_priv->czclk_freq) {
535 int cdclk = cdclk_state->cdclk;
539 switch (cdclk) {
547 MISSING_CASE(cdclk);
574 if (cdclk == 400000) {
578 cdclk) - 1;
580 /* adjust cdclk divider */
600 if (cdclk == 400000)
622 int cdclk = cdclk_state->cdclk;
626 switch (cdclk) {
633 MISSING_CASE(cdclk);
677 static u8 bdw_calc_voltage_level(int cdclk)
679 switch (cdclk) {
699 cdclk_state->cdclk = 800000;
701 cdclk_state->cdclk = 450000;
703 cdclk_state->cdclk = 450000;
705 cdclk_state->cdclk = 540000;
707 cdclk_state->cdclk = 337500;
709 cdclk_state->cdclk = 675000;
716 bdw_calc_voltage_level(cdclk_state->cdclk);
723 int cdclk = cdclk_state->cdclk;
732 "trying to change cdclk frequency with cdclk not enabled\n"))
738 DRM_ERROR("failed to inform pcode about cdclk change\n");
757 switch (cdclk) {
759 MISSING_CASE(cdclk);
788 I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
816 static u8 skl_calc_voltage_level(int cdclk)
818 if (cdclk > 540000)
820 else if (cdclk > 450000)
822 else if (cdclk > 337500)
875 cdclk_state->cdclk = cdclk_state->bypass = cdclk_state->ref;
885 cdclk_state->cdclk = 432000;
888 cdclk_state->cdclk = 308571;
891 cdclk_state->cdclk = 540000;
894 cdclk_state->cdclk = 617143;
903 cdclk_state->cdclk = 450000;
906 cdclk_state->cdclk = 337500;
909 cdclk_state->cdclk = 540000;
912 cdclk_state->cdclk = 675000;
926 skl_calc_voltage_level(cdclk_state->cdclk);
930 static int skl_cdclk_decimal(int cdclk)
932 return DIV_ROUND_CLOSEST(cdclk - 1000, 500);
981 dev_priv->cdclk.hw.vco = vco;
993 dev_priv->cdclk.hw.vco = 0;
1000 int cdclk = cdclk_state->cdclk;
1020 DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n",
1025 /* Choose frequency for this cdclk */
1026 switch (cdclk) {
1028 WARN_ON(cdclk != dev_priv->cdclk.hw.bypass);
1048 if (dev_priv->cdclk.hw.vco != 0 &&
1049 dev_priv->cdclk.hw.vco != vco)
1054 if (dev_priv->cdclk.hw.vco != vco) {
1057 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);
1066 if (dev_priv->cdclk.hw.vco != vco)
1073 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);
1101 intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
1104 if (dev_priv->cdclk.hw.vco == 0 ||
1105 dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass)
1116 skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk);
1122 DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
1124 /* force cdclk programming */
1125 dev_priv->cdclk.hw.cdclk = 0;
1127 dev_priv->cdclk.hw.vco = -1;
1136 if (dev_priv->cdclk.hw.cdclk != 0 &&
1137 dev_priv->cdclk.hw.vco != 0) {
1144 dev_priv->cdclk.hw.vco);
1148 cdclk_state = dev_priv->cdclk.hw;
1153 cdclk_state.cdclk = skl_calc_cdclk(0, cdclk_state.vco);
1154 cdclk_state.voltage_level = skl_calc_voltage_level(cdclk_state.cdclk);
1161 struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
1163 cdclk_state.cdclk = cdclk_state.bypass;
1165 cdclk_state.voltage_level = skl_calc_voltage_level(cdclk_state.cdclk);
1171 { .refclk = 19200, .cdclk = 144000, .divider = 8, .ratio = 60 },
1172 { .refclk = 19200, .cdclk = 288000, .divider = 4, .ratio = 60 },
1173 { .refclk = 19200, .cdclk = 384000, .divider = 3, .ratio = 60 },
1174 { .refclk = 19200, .cdclk = 576000, .divider = 2, .ratio = 60 },
1175 { .refclk = 19200, .cdclk = 624000, .divider = 2, .ratio = 65 },
1180 { .refclk = 19200, .cdclk = 79200, .divider = 8, .ratio = 33 },
1181 { .refclk = 19200, .cdclk = 158400, .divider = 4, .ratio = 33 },
1182 { .refclk = 19200, .cdclk = 316800, .divider = 2, .ratio = 33 },
1187 { .refclk = 19200, .cdclk = 168000, .divider = 4, .ratio = 35 },
1188 { .refclk = 19200, .cdclk = 336000, .divider = 2, .ratio = 35 },
1189 { .refclk = 19200, .cdclk = 528000, .divider = 2, .ratio = 55 },
1191 { .refclk = 24000, .cdclk = 168000, .divider = 4, .ratio = 28 },
1192 { .refclk = 24000, .cdclk = 336000, .divider = 2, .ratio = 28 },
1193 { .refclk = 24000, .cdclk = 528000, .divider = 2, .ratio = 44 },
1198 { .refclk = 19200, .cdclk = 172800, .divider = 2, .ratio = 18 },
1199 { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
1200 { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
1201 { .refclk = 19200, .cdclk = 326400, .divider = 4, .ratio = 68 },
1202 { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
1203 { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
1205 { .refclk = 24000, .cdclk = 180000, .divider = 2, .ratio = 15 },
1206 { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 },
1207 { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
1208 { .refclk = 24000, .cdclk = 324000, .divider = 4, .ratio = 54 },
1209 { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
1210 { .refclk = 24000, .cdclk = 648000, .divider = 2, .ratio = 54 },
1212 { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 9 },
1213 { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
1214 { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
1215 { .refclk = 38400, .cdclk = 326400, .divider = 4, .ratio = 34 },
1216 { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
1217 { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
1223 const struct intel_cdclk_vals *table = dev_priv->cdclk.table;
1227 if (table[i].refclk == dev_priv->cdclk.hw.ref &&
1228 table[i].cdclk >= min_cdclk)
1229 return table[i].cdclk;
1231 WARN(1, "Cannot satisfy minimum cdclk %d with refclk %u\n",
1232 min_cdclk, dev_priv->cdclk.hw.ref);
1236 static int bxt_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
1238 const struct intel_cdclk_vals *table = dev_priv->cdclk.table;
1241 if (cdclk == dev_priv->cdclk.hw.bypass)
1245 if (table[i].refclk == dev_priv->cdclk.hw.ref &&
1246 table[i].cdclk == cdclk)
1247 return dev_priv->cdclk.hw.ref * table[i].ratio;
1249 WARN(1, "cdclk %d not valid for refclk %u\n",
1250 cdclk, dev_priv->cdclk.hw.ref);
1254 static u8 bxt_calc_voltage_level(int cdclk)
1256 return DIV_ROUND_UP(cdclk, 25000);
1259 static u8 cnl_calc_voltage_level(int cdclk)
1261 if (cdclk > 336000)
1263 else if (cdclk > 168000)
1269 static u8 icl_calc_voltage_level(int cdclk)
1271 if (cdclk > 556800)
1273 else if (cdclk > 312000)
1279 static u8 ehl_calc_voltage_level(int cdclk)
1281 if (cdclk > 326400)
1283 else if (cdclk > 312000)
1285 else if (cdclk > 180000)
1372 cdclk_state->cdclk = cdclk_state->bypass;
1399 cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, div);
1407 dev_priv->display.calc_voltage_level(cdclk_state->cdclk);
1419 dev_priv->cdclk.hw.vco = 0;
1424 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref);
1439 dev_priv->cdclk.hw.vco = vco;
1454 dev_priv->cdclk.hw.vco = 0;
1459 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref);
1472 dev_priv->cdclk.hw.vco = vco;
1499 int cdclk = cdclk_state->cdclk;
1520 DRM_ERROR("Failed to inform PCU about cdclk change (err %d, freq %d)\n",
1521 ret, cdclk);
1525 /* cdclk = vco / 2 / div{1,1.5,2,4} */
1526 switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
1528 WARN_ON(cdclk != dev_priv->cdclk.hw.bypass);
1549 if (dev_priv->cdclk.hw.vco != 0 &&
1550 dev_priv->cdclk.hw.vco != vco)
1553 if (dev_priv->cdclk.hw.vco != vco)
1557 if (dev_priv->cdclk.hw.vco != 0 &&
1558 dev_priv->cdclk.hw.vco != vco)
1561 if (dev_priv->cdclk.hw.vco != vco)
1565 val = divider | skl_cdclk_decimal(cdclk) |
1572 if (IS_GEN9_LP(dev_priv) && cdclk >= 500000)
1597 ret, cdclk);
1608 dev_priv->cdclk.hw.voltage_level = cdclk_state->voltage_level;
1614 int cdclk, vco;
1617 intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
1619 if (dev_priv->cdclk.hw.vco == 0 ||
1620 dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass)
1637 /* Make sure this is a legal cdclk value for the platform */
1638 cdclk = bxt_calc_cdclk(dev_priv, dev_priv->cdclk.hw.cdclk);
1639 if (cdclk != dev_priv->cdclk.hw.cdclk)
1642 /* Make sure the VCO is correct for the cdclk */
1643 vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
1644 if (vco != dev_priv->cdclk.hw.vco)
1647 expected = skl_cdclk_decimal(cdclk);
1649 /* Figure out what CD2X divider we should be using for this cdclk */
1650 switch (DIV_ROUND_CLOSEST(dev_priv->cdclk.hw.vco,
1651 dev_priv->cdclk.hw.cdclk)) {
1672 if (IS_GEN9_LP(dev_priv) && dev_priv->cdclk.hw.cdclk >= 500000)
1680 DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
1682 /* force cdclk programming */
1683 dev_priv->cdclk.hw.cdclk = 0;
1686 dev_priv->cdclk.hw.vco = -1;
1695 if (dev_priv->cdclk.hw.cdclk != 0 &&
1696 dev_priv->cdclk.hw.vco != 0)
1699 cdclk_state = dev_priv->cdclk.hw;
1706 cdclk_state.cdclk = bxt_calc_cdclk(dev_priv, 0);
1707 cdclk_state.vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk_state.cdclk);
1709 dev_priv->display.calc_voltage_level(cdclk_state.cdclk);
1716 struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
1718 cdclk_state.cdclk = cdclk_state.bypass;
1721 dev_priv->display.calc_voltage_level(cdclk_state.cdclk);
1730 * Initialize CDCLK. This consists mainly of initializing dev_priv->cdclk.hw and
1769 return a->cdclk != b->cdclk ||
1791 return a->cdclk != b->cdclk &&
1827 swap(state->cdclk.logical, dev_priv->cdclk.logical);
1828 swap(state->cdclk.actual, dev_priv->cdclk.actual);
1835 context, cdclk_state->cdclk, cdclk_state->vco,
1853 if (!intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_state))
1863 if (WARN(intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_state),
1864 "cdclk state doesn't match!\n")) {
1865 intel_dump_cdclk_state(&dev_priv->cdclk.hw, "[hw state]");
1886 if (pipe == INVALID_PIPE || old_state->cdclk <= new_state->cdclk)
1906 if (pipe != INVALID_PIPE && old_state->cdclk > new_state->cdclk)
1952 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
1958 * there may be audio corruption or screen corruption." This cdclk
1982 * "For DP audio configuration, cdclk frequency shall be set to
2025 DRM_DEBUG_KMS("required cdclk (%d kHz) exceeds max (%d kHz)\n",
2061 min_cdclk = state->cdclk.force_min_cdclk;
2122 int min_cdclk, cdclk;
2128 cdclk = vlv_calc_cdclk(dev_priv, min_cdclk);
2130 state->cdclk.logical.cdclk = cdclk;
2131 state->cdclk.logical.voltage_level =
2132 vlv_calc_voltage_level(dev_priv, cdclk);
2135 cdclk = vlv_calc_cdclk(dev_priv, state->cdclk.force_min_cdclk);
2137 state->cdclk.actual.cdclk = cdclk;
2138 state->cdclk.actual.voltage_level =
2139 vlv_calc_voltage_level(dev_priv, cdclk);
2141 state->cdclk.actual = state->cdclk.logical;
2149 int min_cdclk, cdclk;
2159 cdclk = bdw_calc_cdclk(min_cdclk);
2161 state->cdclk.logical.cdclk = cdclk;
2162 state->cdclk.logical.voltage_level =
2163 bdw_calc_voltage_level(cdclk);
2166 cdclk = bdw_calc_cdclk(state->cdclk.force_min_cdclk);
2168 state->cdclk.actual.cdclk = cdclk;
2169 state->cdclk.actual.voltage_level =
2170 bdw_calc_voltage_level(cdclk);
2172 state->cdclk.actual = state->cdclk.logical;
2185 vco = state->cdclk.logical.vco;
2198 * clock for eDP. This will affect cdclk as well.
2216 int min_cdclk, cdclk, vco;
2228 cdclk = skl_calc_cdclk(min_cdclk, vco);
2230 state->cdclk.logical.vco = vco;
2231 state->cdclk.logical.cdclk = cdclk;
2232 state->cdclk.logical.voltage_level =
2233 skl_calc_voltage_level(cdclk);
2236 cdclk = skl_calc_cdclk(state->cdclk.force_min_cdclk, vco);
2238 state->cdclk.actual.vco = vco;
2239 state->cdclk.actual.cdclk = cdclk;
2240 state->cdclk.actual.voltage_level =
2241 skl_calc_voltage_level(cdclk);
2243 state->cdclk.actual = state->cdclk.logical;
2252 int min_cdclk, min_voltage_level, cdclk, vco;
2262 cdclk = bxt_calc_cdclk(dev_priv, min_cdclk);
2263 vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
2265 state->cdclk.logical.vco = vco;
2266 state->cdclk.logical.cdclk = cdclk;
2267 state->cdclk.logical.voltage_level =
2269 dev_priv->display.calc_voltage_level(cdclk));
2272 cdclk = bxt_calc_cdclk(dev_priv, state->cdclk.force_min_cdclk);
2273 vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
2275 state->cdclk.actual.vco = vco;
2276 state->cdclk.actual.cdclk = cdclk;
2277 state->cdclk.actual.voltage_level =
2278 dev_priv->display.calc_voltage_level(cdclk);
2280 state->cdclk.actual = state->cdclk.logical;
2330 * We can't change the cdclk frequency, but we still want to
2332 * the actual cdclk frequency.
2352 * Writes to dev_priv->cdclk.{actual,logical} must protected
2356 if (intel_cdclk_changed(&dev_priv->cdclk.actual,
2357 &state->cdclk.actual)) {
2365 } else if (intel_cdclk_changed(&dev_priv->cdclk.logical,
2366 &state->cdclk.logical)) {
2376 &dev_priv->cdclk.actual,
2377 &state->cdclk.actual)) {
2395 state->cdclk.pipe = pipe;
2397 DRM_DEBUG_KMS("Can change cdclk with pipe %c active\n",
2399 } else if (intel_cdclk_needs_modeset(&dev_priv->cdclk.actual,
2400 &state->cdclk.actual)) {
2401 /* All pipes must be switched off while we change the cdclk. */
2406 state->cdclk.pipe = INVALID_PIPE;
2408 DRM_DEBUG_KMS("Modeset required for cdclk change\n");
2411 DRM_DEBUG_KMS("New cdclk calculated to be logical %u kHz, actual %u kHz\n",
2412 state->cdclk.logical.cdclk,
2413 state->cdclk.actual.cdclk);
2415 state->cdclk.logical.voltage_level,
2416 state->cdclk.actual.voltage_level);
2449 if (dev_priv->cdclk.hw.ref == 24000)
2454 if (dev_priv->cdclk.hw.ref == 24000)
2468 * Use the lower (vco 8640) cdclk values as a
2506 /* otherwise assume cdclk is fixed */
2507 dev_priv->max_cdclk_freq = dev_priv->cdclk.hw.cdclk;
2527 dev_priv->display.get_cdclk(dev_priv, &dev_priv->cdclk.hw);
2532 * of cdclk that generates 4MHz reference clock freq which is used to
2533 * generate GMBus clock. This will vary with the cdclk freq.
2537 DIV_ROUND_UP(dev_priv->cdclk.hw.cdclk, 1000));
2641 dev_priv->cdclk.table = icl_cdclk_table;
2646 dev_priv->cdclk.table = icl_cdclk_table;
2651 dev_priv->cdclk.table = cnl_cdclk_table;
2657 dev_priv->cdclk.table = glk_cdclk_table;
2659 dev_priv->cdclk.table = bxt_cdclk_table;