Lines Matching defs:dividers
547 pp_atomctrl_clock_dividers_vi dividers;
558 /* get the engine clock dividers for this clock value*/
559 result = atomctrl_get_engine_pll_dividers_vi(hwmgr, engine_clock, ÷rs);
562 "Error retrieving Engine Clock dividers from VBIOS.", return result);
567 reference_divider = 1 + dividers.uc_pll_ref_div;
570 fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF;
574 CG_SPLL_FUNC_CNTL, SPLL_REF_DIV, dividers.uc_pll_ref_div);
576 CG_SPLL_FUNC_CNTL, SPLL_PDIV_A, dividers.uc_pll_post_div);
590 uint32_t vcoFreq = engine_clock * dividers.uc_pll_post_div;
616 sclk->SclkDid = (uint8_t)dividers.pll_post_divider;
1185 struct pp_atomctrl_clock_dividers_vi dividers;
1202 /* get the engine clock dividers for this clock value*/
1204 table->ACPILevel.SclkFrequency, ÷rs);
1207 "Error retrieving Engine Clock dividers from VBIOS.",
1211 table->ACPILevel.SclkDid = (uint8_t)dividers.pll_post_divider;
1318 pp_atomctrl_clock_dividers_vi dividers;
1347 ÷rs);
1353 table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;
1356 table->UvdLevel[count].DclkFrequency, ÷rs);
1362 (uint8_t)dividers.pll_post_divider;
1378 pp_atomctrl_clock_dividers_vi dividers;
1405 table->VceLevel[count].Frequency, ÷rs);
1410 table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1423 pp_atomctrl_clock_dividers_vi dividers;
1450 table->AcpLevel[count].Frequency, ÷rs);
1454 table->AcpLevel[count].Divider = (uint8_t)dividers.pll_post_divider;