powerplay/smumgr/amdgpu_smu10_smumgr.c

130 	PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0,
132 	PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0,
136 			upper_32_bits(priv->smu_tables.entry[table_id].mc_addr));
139 			lower_32_bits(priv->smu_tables.entry[table_id].mc_addr));
142 			priv->smu_tables.entry[table_id].table_id);
147 	memcpy(table, (uint8_t *)priv->smu_tables.entry[table_id].table,
148 			priv->smu_tables.entry[table_id].size);
162 	PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0,
164 	PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0,
167 	memcpy(priv->smu_tables.entry[table_id].table, table,
168 			priv->smu_tables.entry[table_id].size);
174 			upper_32_bits(priv->smu_tables.entry[table_id].mc_addr));
177 			lower_32_bits(priv->smu_tables.entry[table_id].mc_addr));
180 			priv->smu_tables.entry[table_id].table_id);
208 		amdgpu_bo_free_kernel(&priv->smu_tables.entry[SMU10_WMTABLE].handle,
209 					&priv->smu_tables.entry[SMU10_WMTABLE].mc_addr,
210 					&priv->smu_tables.entry[SMU10_WMTABLE].table);
211 		amdgpu_bo_free_kernel(&priv->smu_tables.entry[SMU10_CLOCKTABLE].handle,
212 					&priv->smu_tables.entry[SMU10_CLOCKTABLE].mc_addr,
213 					&priv->smu_tables.entry[SMU10_CLOCKTABLE].table);
256 			&priv->smu_tables.entry[SMU10_WMTABLE].handle,
257 			&priv->smu_tables.entry[SMU10_WMTABLE].mc_addr,
258 			&priv->smu_tables.entry[SMU10_WMTABLE].table);
263 	priv->smu_tables.entry[SMU10_WMTABLE].version = 0x01;
264 	priv->smu_tables.entry[SMU10_WMTABLE].size = sizeof(Watermarks_t);
265 	priv->smu_tables.entry[SMU10_WMTABLE].table_id = TABLE_WATERMARKS;
272 			&priv->smu_tables.entry[SMU10_CLOCKTABLE].handle,
273 			&priv->smu_tables.entry[SMU10_CLOCKTABLE].mc_addr,
274 			&priv->smu_tables.entry[SMU10_CLOCKTABLE].table);
279 	priv->smu_tables.entry[SMU10_CLOCKTABLE].version = 0x01;
280 	priv->smu_tables.entry[SMU10_CLOCKTABLE].size = sizeof(DpmClocks_t);
281 	priv->smu_tables.entry[SMU10_CLOCKTABLE].table_id = TABLE_DPMCLOCKS;
286 	amdgpu_bo_free_kernel(&priv->smu_tables.entry[SMU10_WMTABLE].handle,
287 				&priv->smu_tables.entry[SMU10_WMTABLE].mc_addr,
288 				&priv->smu_tables.entry[SMU10_WMTABLE].table);