powerplay/smumgr/amdgpu_polaris10_smumgr.c

984 	struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
986 	struct smu7_dpm_table *dpm_table = &hw_data->dpm_table;
990 	uint8_t pcie_entry_cnt = (uint8_t) hw_data->dpm_table.pcie_speed_table.count;
1025 	hw_data->dpm_level_enable_mask.sclk_dpm_enable_mask =
1038 		while (hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
1039 				((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1043 		while (hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
1044 				((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1049 				((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1131 	struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
1133 	struct smu7_dpm_table *dpm_table = &hw_data->dpm_table;
1169 	hw_data->dpm_level_enable_mask.mclk_dpm_enable_mask =
1369 	struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
1375 	for (i = 0; i < hw_data->dpm_table.sclk_table.count; i++) {
1376 		for (j = 0; j < hw_data->dpm_table.mclk_table.count; j++) {
1378 					hw_data->dpm_table.sclk_table.dpm_levels[i].value,
1379 					hw_data->dpm_table.mclk_table.dpm_levels[j].value,
1382 				result = atomctrl_set_ac_timing_ai(hwmgr, hw_data->dpm_table.mclk_table.dpm_levels[j].value, j);
1488 	struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
1498 				hw_data->vbios_boot_state.sclk_bootup_value) {
1507 				hw_data->vbios_boot_state.mclk_bootup_value) {
1828 	struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
1840 	if (SMU7_VOLTAGE_CONTROL_NONE != hw_data->voltage_control)
1852 	if (hw_data->is_memory_gddr5)
1855 	if (hw_data->ulv_supported && table_info->us_ulv_voltage_offset) {
1942 	hw_data->vr_config = table->VRConfig;
1993 	for (i = 0; i <= hw_data->dpm_table.pcie_speed_table.count; i++) {