Lines Matching defs:dividers

851 	struct pp_atomctrl_clock_dividers_ai dividers;
859 /* get the engine clock dividers for this clock value */
860 result = atomctrl_get_engine_pll_dividers_ai(hwmgr, clock, &dividers);
862 sclk_setting->Fcw_int = dividers.usSclk_fcw_int;
863 sclk_setting->Fcw_frac = dividers.usSclk_fcw_frac;
864 sclk_setting->Pcc_fcw_int = dividers.usPcc_fcw_int;
865 sclk_setting->PllRange = dividers.ucSclkPllRange;
867 sclk_setting->Pcc_up_slew_rate = dividers.usPcc_fcw_slew_frac;
869 sclk_setting->SSc_En = dividers.ucSscEnable;
870 sclk_setting->Fcw1_int = dividers.usSsc_fcw1_int;
871 sclk_setting->Fcw1_frac = dividers.usSsc_fcw1_frac;
872 sclk_setting->Sclk_ss_slew_rate = dividers.usSsc_fcw_slew_frac;
1230 PP_ASSERT_WITH_CODE(result == 0, "Error retrieving Engine Clock dividers from VBIOS.", return result);
1296 struct pp_atomctrl_clock_dividers_vi dividers;
1328 table->VceLevel[count].Frequency, &dividers);
1333 table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1402 struct pp_atomctrl_clock_dividers_vi dividers;
1433 table->UvdLevel[count].VclkFrequency, &dividers);
1437 table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;
1440 table->UvdLevel[count].DclkFrequency, &dividers);
1444 table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;
1836 pp_atomctrl_clock_dividers_vi dividers;
1994 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, smu_data->bif_sclk_table[i], &dividers);
1998 table->Ulv.BifSclkDfs = PP_HOST_TO_SMC_US((USHORT)(dividers.pll_post_divider));
2000 table->LinkLevel[i-1].BifSclkDfs = PP_HOST_TO_SMC_US((USHORT)(dividers.pll_post_divider));