powerplay/hwmgr/amdgpu_vega10_processpptables.c

74 		const ATOM_Vega10_POWERPLAYTABLE *powerplay_table)
78 	state_arrays = (ATOM_Vega10_State_Array *)(((unsigned long)powerplay_table) +
79 		le16_to_cpu(powerplay_table->usStateArrayOffset));
81 	PP_ASSERT_WITH_CODE((powerplay_table->sHeader.format_revision >=
84 	PP_ASSERT_WITH_CODE(powerplay_table->usStateArrayOffset,
86 	PP_ASSERT_WITH_CODE(powerplay_table->sHeader.structuresize > 0,
126 		const ATOM_Vega10_POWERPLAYTABLE *powerplay_table)
135 			(((unsigned long)powerplay_table) +
136 			le16_to_cpu(powerplay_table->usThermalControllerOffset));
138 	PP_ASSERT_WITH_CODE((powerplay_table->usThermalControllerOffset != 0),
166 	if (!powerplay_table->usFanTableOffset)
170 			(((unsigned long)powerplay_table) +
171 			le16_to_cpu(powerplay_table->usFanTableOffset));
314 		const ATOM_Vega10_POWERPLAYTABLE *powerplay_table)
318 			(((unsigned long) powerplay_table) +
319 			le16_to_cpu(powerplay_table->usGfxclkDependencyTableOffset));
330 	if (powerplay_table->ulMaxODEngineClock > VEGA10_ENGINECLOCK_HARDMAX &&
336 			le32_to_cpu(powerplay_table->ulMaxODEngineClock);
338 			le32_to_cpu(powerplay_table->ulMaxODMemoryClock);
909 		const ATOM_Vega10_POWERPLAYTABLE *powerplay_table)
917 			(((unsigned long) powerplay_table) +
918 			le16_to_cpu(powerplay_table->usMMDependencyTableOffset));
921 			(((unsigned long) powerplay_table) +
922 			le16_to_cpu(powerplay_table->usPowerTuneTableOffset));
925 			(((unsigned long) powerplay_table) +
926 			le16_to_cpu(powerplay_table->usSocclkDependencyTableOffset));
929 			(((unsigned long) powerplay_table) +
930 			le16_to_cpu(powerplay_table->usGfxclkDependencyTableOffset));
933 			(((unsigned long) powerplay_table) +
934 			le16_to_cpu(powerplay_table->usDcefclkDependencyTableOffset));
937 			(((unsigned long) powerplay_table) +
938 			le16_to_cpu(powerplay_table->usMclkDependencyTableOffset));
941 			(((unsigned long) powerplay_table) +
942 			le16_to_cpu(powerplay_table->usHardLimitTableOffset));
945 			(((unsigned long) powerplay_table) +
946 			le16_to_cpu(powerplay_table->usPCIETableOffset));
949 			(((unsigned long) powerplay_table) +
950 			le16_to_cpu(powerplay_table->usPixclkDependencyTableOffset));
953 			(((unsigned long) powerplay_table) +
954 			le16_to_cpu(powerplay_table->usPhyClkDependencyTableOffset));
957 			(((unsigned long) powerplay_table) +
958 			le16_to_cpu(powerplay_table->usDispClkDependencyTableOffset));
970 	if (powerplay_table->usMMDependencyTableOffset)
975 	if (!result && powerplay_table->usPowerTuneTableOffset)
980 	if (!result && powerplay_table->usSocclkDependencyTableOffset)
985 	if (!result && powerplay_table->usGfxclkDependencyTableOffset)
990 	if (!result && powerplay_table->usPixclkDependencyTableOffset)
996 	if (!result && powerplay_table->usPhyClkDependencyTableOffset)
1002 	if (!result && powerplay_table->usDispClkDependencyTableOffset)
1008 	if (!result && powerplay_table->usDcefclkDependencyTableOffset)
1013 	if (!result && powerplay_table->usMclkDependencyTableOffset)
1018 	if (!result && powerplay_table->usPCIETableOffset)
1023 	if (!result && powerplay_table->usHardLimitTableOffset)
1101 		const ATOM_Vega10_POWERPLAYTABLE *powerplay_table)
1109 		le16_to_cpu(powerplay_table->usUlvVoltageOffset);
1112 			le16_to_cpu(powerplay_table->usUlvSmnclkDid);
1114 			le16_to_cpu(powerplay_table->usUlvMp1clkDid);
1116 			le16_to_cpu(powerplay_table->usUlvGfxclkBypass);
1118 			le16_to_cpu(powerplay_table->usGfxclkSlewRate);
1120 			le16_to_cpu(powerplay_table->ucGfxVoltageMode);
1122 			le16_to_cpu(powerplay_table->ucSocVoltageMode);
1124 			le16_to_cpu(powerplay_table->ucUclkVoltageMode);
1126 			le16_to_cpu(powerplay_table->ucUvdVoltageMode);
1128 			le16_to_cpu(powerplay_table->ucVceVoltageMode);
1130 			le16_to_cpu(powerplay_table->ucMp0VoltageMode);
1132 			le16_to_cpu(powerplay_table->ucDcefVoltageMode);
1141 		le16_to_cpu(powerplay_table->usPowerControlLimit);
1157 	if (powerplay_table->usVddcLookupTableOffset) {
1160 				(((unsigned long)powerplay_table) +
1161 				le16_to_cpu(powerplay_table->usVddcLookupTableOffset));
1166 	if (powerplay_table->usVddmemLookupTableOffset) {
1169 				(((unsigned long)powerplay_table) +
1170 				le16_to_cpu(powerplay_table->usVddmemLookupTableOffset));
1175 	if (powerplay_table->usVddciLookupTableOffset) {
1178 				(((unsigned long)powerplay_table) +
1179 				le16_to_cpu(powerplay_table->usVddciLookupTableOffset));
1190 	const ATOM_Vega10_POWERPLAYTABLE *powerplay_table;
1197 	powerplay_table = get_powerplay_table(hwmgr);
1199 	PP_ASSERT_WITH_CODE((powerplay_table != NULL),
1202 	result = check_powerplay_tables(hwmgr, powerplay_table);
1208 				   le32_to_cpu(powerplay_table->ulPlatformCaps));
1213 	result = init_thermal_controller(hwmgr, powerplay_table);
1218 	result = init_over_drive_limits(hwmgr, powerplay_table);
1223 	result = init_powerplay_extended_tables(hwmgr, powerplay_table);
1228 	result = init_dpm_2_parameters(hwmgr, powerplay_table);
1385 	const ATOM_Vega10_POWERPLAYTABLE *powerplay_table;
1387 	powerplay_table = get_powerplay_table(hwmgr);
1389 	PP_ASSERT_WITH_CODE((powerplay_table != NULL),
1392 	result = check_powerplay_tables(hwmgr, powerplay_table);
1399 			0 != (le32_to_cpu(powerplay_table->ulPlatformCaps) & ATOM_VEGA10_PP_PLATFORM_CAP_BACO),