amd/powerplay/amdgpu_renoir_ppt.c

175 static int renoir_get_metrics_table(struct smu_context *smu,
178 	struct smu_table_context *smu_table= &smu->smu_table;
181 	mutex_lock(&smu->metrics_lock);
183 		ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
187 			mutex_unlock(&smu->metrics_lock);
194 	mutex_unlock(&smu->metrics_lock);
199 static int renoir_tables_init(struct smu_context *smu, struct smu_table *tables)
201 	struct smu_table_context *smu_table = &smu->smu_table;
230 static int renoir_get_dpm_clk_limited(struct smu_context *smu, enum smu_clk_type clk_type,
233 	DpmClocks_t *clk_table = smu->smu_table.clocks_table;
243 static int renoir_print_clk_levels(struct smu_context *smu,
248 	DpmClocks_t *clk_table = smu->smu_table.clocks_table;
256 	ret = renoir_get_metrics_table(smu, &metrics);
265 		ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK, &min, &max, false);
313 static enum amd_pm_state_type renoir_get_current_power_state(struct smu_context *smu)
316 	struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
343 static int renoir_dpm_set_uvd_enable(struct smu_context *smu, bool enable)
345 	struct smu_power_context *smu_power = &smu->smu_power;
351 		if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
352 			ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0);
358 		if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
359 			ret = smu_send_smc_msg(smu, SMU_MSG_PowerDownVcn);
369 static int renoir_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
371 	struct smu_power_context *smu_power = &smu->smu_power;
376 		if (smu_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
377 			ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0);
383 		if (smu_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
384 			ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0);
394 static int renoir_get_current_clk_freq_by_table(struct smu_context *smu,
401 	ret = renoir_get_metrics_table(smu, &metrics);
405 	clk_id = smu_clk_get_index(smu, clk_type);
414 static int renoir_force_dpm_limit_value(struct smu_context *smu, bool highest)
428 		ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq, false);
433 		ret = smu_set_soft_freq_range(smu, clk_type, force_freq, force_freq);
441 static int renoir_unforce_dpm_levels(struct smu_context *smu) {
457 		if (!smu_feature_is_enabled(smu, clk_feature_map[i].feature))
462 		ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq, false);
466 		ret = smu_set_soft_freq_range(smu, clk_type, min_freq, max_freq);
474 static int renoir_get_gpu_temperature(struct smu_context *smu, uint32_t *value)
482 	ret = renoir_get_metrics_table(smu, &metrics);
492 static int renoir_get_current_activity_percent(struct smu_context *smu,
502 	ret = renoir_get_metrics_table(smu, &metrics);
518 static int renoir_get_workload_type(struct smu_context *smu, uint32_t profile)
546 static int renoir_get_profiling_clk_mask(struct smu_context *smu,
577 static int renoir_get_dpm_clock_table(struct smu_context *smu, struct dpm_clocks *clock_table)
579 	DpmClocks_t *table = smu->smu_table.clocks_table;
608 static int renoir_force_clk_levels(struct smu_context *smu,
614 	DpmClocks_t *clk_table = smu->smu_table.clocks_table;
627 		ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK, &min_freq, &max_freq, false);
630 		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk,
635 		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk,
644 		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxSocclkByFreq, max_freq);
647 		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinSocclkByFreq, min_freq);
655 		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxFclkByFreq, max_freq);
658 		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinFclkByFreq, min_freq);
669 static int renoir_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
675 		pr_err("Invalid power profile mode %d\n", smu->power_profile_mode);
680 	workload_type = smu_workload_get_type(smu, smu->power_profile_mode);
682 		pr_err("Unsupported power profile mode %d on RENOIR\n",smu->power_profile_mode);
686 	ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
693 	smu->power_profile_mode = profile_mode;
698 static int renoir_set_peak_clock_by_device(struct smu_context *smu)
703 	ret = smu_get_dpm_freq_range(smu, SMU_SCLK, NULL, &sclk_freq, false);
707 	ret = smu_set_soft_freq_range(smu, SMU_SCLK, sclk_freq, sclk_freq);
711 	ret = smu_get_dpm_freq_range(smu, SMU_UCLK, NULL, &uclk_freq, false);
715 	ret = smu_set_soft_freq_range(smu, SMU_UCLK, uclk_freq, uclk_freq);
722 static int renoir_set_performance_level(struct smu_context *smu,
730 		ret = smu_force_dpm_limit_value(smu, true);
733 		ret = smu_force_dpm_limit_value(smu, false);
737 		ret = smu_unforce_dpm_levels(smu);
741 		ret = smu_get_profiling_clk_mask(smu, level,
747 		smu_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask, false);
748 		smu_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask, false);
749 		smu_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask, false);
752 		ret = renoir_set_peak_clock_by_device(smu);
762 /* save watermark settings into pplib smu structure,
763  * also pass data to smu controller
766 		struct smu_context *smu,
781 	/* save into smu->smu_table.tables[SMU_TABLE_WATERMARKS]->cpu_addr*/
816 	/* pass data to smu controller */
817 	if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
818 			!(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
819 		ret = smu_write_watermarks_table(smu);
824 		smu->watermarks_bitmap |= WATERMARKS_LOADED;
830 static int renoir_get_power_profile_mode(struct smu_context *smu,
844 	if (!smu->pm_enabled || !buf)
852 		workload_type = smu_workload_get_type(smu, i);
857 			i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
863 static int renoir_read_sensor(struct smu_context *smu,
872 	mutex_lock(&smu->sensor_lock);
875 		ret = renoir_get_current_activity_percent(smu, sensor, (uint32_t *)data);
879 		ret = renoir_get_gpu_temperature(smu, (uint32_t *)data);
883 		ret = smu_v12_0_read_sensor(smu, sensor, data, size);
885 	mutex_unlock(&smu->sensor_lock);
933 void renoir_set_ppt_funcs(struct smu_context *smu)
935 	smu->ppt_funcs = &renoir_ppt_funcs;
936 	smu->smc_if_version = SMU12_DRIVER_IF_VERSION;
937 	smu->is_apu = true;