Lines Matching refs:x14
212 #define CB_COLOR0_PITCH__FMASK_TILE_MAX__SHIFT 0x14
216 #define CB_COLOR1_PITCH__FMASK_TILE_MAX__SHIFT 0x14
220 #define CB_COLOR2_PITCH__FMASK_TILE_MAX__SHIFT 0x14
224 #define CB_COLOR3_PITCH__FMASK_TILE_MAX__SHIFT 0x14
228 #define CB_COLOR4_PITCH__FMASK_TILE_MAX__SHIFT 0x14
232 #define CB_COLOR5_PITCH__FMASK_TILE_MAX__SHIFT 0x14
236 #define CB_COLOR6_PITCH__FMASK_TILE_MAX__SHIFT 0x14
240 #define CB_COLOR7_PITCH__FMASK_TILE_MAX__SHIFT 0x14
314 #define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
350 #define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
386 #define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
422 #define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
458 #define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
494 #define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
530 #define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
566 #define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
940 #define CB_TARGET_MASK__TARGET5_ENABLE__SHIFT 0x14
956 #define CB_SHADER_MASK__OUTPUT5_ENABLE__SHIFT 0x14
974 #define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE__SHIFT 0x14
1078 #define CB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
1204 #define CB_DEBUG_BUS_18__DCS_READ_CC_PENDING__SHIFT 0x14
1260 #define CB_DEBUG_BUS_20__CC_WRREQ_FIFO_EMPTY__SHIFT 0x14
1368 #define CP_RB0_CNTL__MIN_AVAILSZ__SHIFT 0x14
1386 #define CP_RB_CNTL__MIN_AVAILSZ__SHIFT 0x14
1402 #define CP_RB1_CNTL__MIN_AVAILSZ__SHIFT 0x14
1418 #define CP_RB2_CNTL__MIN_AVAILSZ__SHIFT 0x14
1476 #define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14
1506 #define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14
1536 #define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14
1566 #define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14
1596 #define CP_INT_STATUS__CNTX_EMPTY_INT_STAT__SHIFT 0x14
1626 #define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT__SHIFT 0x14
1656 #define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT__SHIFT 0x14
1686 #define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT__SHIFT 0x14
2460 #define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX__SHIFT 0x14
2584 #define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY__SHIFT 0x14
2712 #define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY__SHIFT 0x14
2766 #define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET__SHIFT 0x14
2800 #define CPG_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
2820 #define CPC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
2840 #define CPF_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
3108 #define CP_ME_MC_WADDR_HI__MTYPE__SHIFT 0x14
3122 #define CP_ME_MC_RADDR_HI__MTYPE__SHIFT 0x14
3136 #define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT 0x14
3150 #define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT 0x14
3258 #define CP_DMA_ME_CONTROL__DST_SELECT__SHIFT 0x14
3300 #define CP_DMA_PFP_CONTROL__DST_SELECT__SHIFT 0x14
3492 #define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x14
3552 #define CP_STALLED_STAT3__ATCL1_WAITING_ON_TRANS__SHIFT 0x14
3580 #define CP_BUSY_STAT__PIPE_STATS_BUSY__SHIFT 0x14
3608 #define CP_STAT__INTERRUPT_BUSY__SHIFT 0x14
3660 #define CP_ME_CNTL__ME_PIPE0_RESET__SHIFT 0x14
3678 #define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS__SHIFT 0x14
3838 #define CP_INT_STAT_DEBUG__CNTX_EMPTY_INT_ASSERTED__SHIFT 0x14
3964 #define CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE__SHIFT 0x14
3990 #define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT 0x14
4200 #define DB_Z_INFO__TILE_MODE_INDEX__SHIFT 0x14
4218 #define DB_STENCIL_INFO__TILE_MODE_INDEX__SHIFT 0x14
4272 #define DB_COUNT_CONTROL__DBFAIL_ENABLE__SHIFT 0x14
4370 #define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS__SHIFT 0x14
4482 #define DB_DEPTH_CONTROL__STENCILFUNC_BF__SHIFT 0x14
4498 #define DB_STENCIL_CONTROL__STENCILZFAIL_BF__SHIFT 0x14
4516 #define DB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
4526 #define DB_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
4536 #define DB_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
4546 #define DB_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
4708 #define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE__SHIFT 0x14
4758 #define DB_WATERMARKS__DEPTH_CACHELINE_FREE__SHIFT 0x14
4900 #define CC_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14
4910 #define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14
4924 #define GB_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
4946 #define CC_RB_DAISY_CHAIN__RB_5__SHIFT 0x14
5402 #define GB_EDC_MODE__DED_MODE__SHIFT 0x14
5524 #define GRBM_STATUS__SX_BUSY__SHIFT 0x14
5682 #define GRBM_SOFT_RESET__SOFT_RESET_CAC__SHIFT 0x14
5762 #define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY1__SHIFT 0x14
5768 #define GRBM_READ_ERROR__READ_PIPEID__SHIFT 0x14
5780 #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF__SHIFT 0x14
5834 #define GRBM_WRITE_ERROR__WRITE_PIPEID__SHIFT 0x14
5860 #define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x14
5898 #define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x14
5936 #define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14
5960 #define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14
5984 #define GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14
6008 #define GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14
6310 #define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG__SHIFT 0x14
6354 #define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0__SHIFT 0x14
6380 #define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT__SHIFT 0x14
6548 #define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS__SHIFT 0x14
6576 #define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
6586 #define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
6594 #define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
6598 #define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
6622 #define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES__SHIFT 0x14
6644 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y__SHIFT 0x14
6660 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y__SHIFT 0x14
6676 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y__SHIFT 0x14
6692 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y__SHIFT 0x14
6708 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y__SHIFT 0x14
6724 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y__SHIFT 0x14
6740 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y__SHIFT 0x14
6756 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y__SHIFT 0x14
6772 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y__SHIFT 0x14
6788 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y__SHIFT 0x14
6804 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y__SHIFT 0x14
6820 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y__SHIFT 0x14
6836 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y__SHIFT 0x14
6852 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y__SHIFT 0x14
6868 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y__SHIFT 0x14
6884 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y__SHIFT 0x14
6900 #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5__SHIFT 0x14
6916 #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13__SHIFT 0x14
7030 #define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE__SHIFT 0x14
7064 #define PA_SC_RASTER_CONFIG__SC_YSEL__SHIFT 0x14
7376 #define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY__SHIFT 0x14
7444 #define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
7616 #define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full__SHIFT 0x14
7650 #define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive__SHIFT 0x14
7684 #define CLIPPER_DEBUG_REG02__clip_to_clipga_extra_bc_coords__SHIFT 0x14
7712 #define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_state_var_indx__SHIFT 0x14
7746 #define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_state_var_indx__SHIFT 0x14
7780 #define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_state_var_indx__SHIFT 0x14
7814 #define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_state_var_indx__SHIFT 0x14
7866 #define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x14
7892 #define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_vert__SHIFT 0x14
7958 #define CLIPPER_DEBUG_REG14__clprim_in_back_first_prim_of_slot__SHIFT 0x14
7990 #define CLIPPER_DEBUG_REG16__sm0_current_state__SHIFT 0x14
8014 #define CLIPPER_DEBUG_REG17__sm1_current_state__SHIFT 0x14
8038 #define CLIPPER_DEBUG_REG18__sm2_current_state__SHIFT 0x14
8062 #define CLIPPER_DEBUG_REG19__sm3_current_state__SHIFT 0x14
8102 #define SXIFCCG_DEBUG_REG1__aux_sel__SHIFT 0x14
8172 #define SETUP_DEBUG_REG0__su_cntl_busy__SHIFT 0x14
8208 #define SETUP_DEBUG_REG4__dealloc_slot_gated__SHIFT 0x14
8312 #define COMPUTE_PGM_RSRC1__PRIV__SHIFT 0x14
8512 #define RLC_MC_CNTL__RDNFO_URG__SHIFT 0x14
8768 #define RLC_PG_CNTL__QUICK_PG_ENABLE__SHIFT 0x14
8932 #define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE0_MASTER_MASK__SHIFT 0x14
8982 #define RLC_SERDES_NONCU_MASTER_BUSY__SPARE0_MASTER_BUSY__SHIFT 0x14
9030 #define RLC_GPM_PERF_COUNT_0__ENABLE__SHIFT 0x14
9046 #define RLC_GPM_PERF_COUNT_1__ENABLE__SHIFT 0x14
9560 #define SPI_PS_INPUT_CNTL_0__USE_DEFAULT_ATTR1__SHIFT 0x14
9584 #define SPI_PS_INPUT_CNTL_1__USE_DEFAULT_ATTR1__SHIFT 0x14
9608 #define SPI_PS_INPUT_CNTL_2__USE_DEFAULT_ATTR1__SHIFT 0x14
9632 #define SPI_PS_INPUT_CNTL_3__USE_DEFAULT_ATTR1__SHIFT 0x14
9656 #define SPI_PS_INPUT_CNTL_4__USE_DEFAULT_ATTR1__SHIFT 0x14
9680 #define SPI_PS_INPUT_CNTL_5__USE_DEFAULT_ATTR1__SHIFT 0x14
9704 #define SPI_PS_INPUT_CNTL_6__USE_DEFAULT_ATTR1__SHIFT 0x14
9728 #define SPI_PS_INPUT_CNTL_7__USE_DEFAULT_ATTR1__SHIFT 0x14
9752 #define SPI_PS_INPUT_CNTL_8__USE_DEFAULT_ATTR1__SHIFT 0x14
9776 #define SPI_PS_INPUT_CNTL_9__USE_DEFAULT_ATTR1__SHIFT 0x14
9800 #define SPI_PS_INPUT_CNTL_10__USE_DEFAULT_ATTR1__SHIFT 0x14
9824 #define SPI_PS_INPUT_CNTL_11__USE_DEFAULT_ATTR1__SHIFT 0x14
9848 #define SPI_PS_INPUT_CNTL_12__USE_DEFAULT_ATTR1__SHIFT 0x14
9872 #define SPI_PS_INPUT_CNTL_13__USE_DEFAULT_ATTR1__SHIFT 0x14
9896 #define SPI_PS_INPUT_CNTL_14__USE_DEFAULT_ATTR1__SHIFT 0x14
9920 #define SPI_PS_INPUT_CNTL_15__USE_DEFAULT_ATTR1__SHIFT 0x14
9944 #define SPI_PS_INPUT_CNTL_16__USE_DEFAULT_ATTR1__SHIFT 0x14
9968 #define SPI_PS_INPUT_CNTL_17__USE_DEFAULT_ATTR1__SHIFT 0x14
9992 #define SPI_PS_INPUT_CNTL_18__USE_DEFAULT_ATTR1__SHIFT 0x14
10016 #define SPI_PS_INPUT_CNTL_19__USE_DEFAULT_ATTR1__SHIFT 0x14
10036 #define SPI_PS_INPUT_CNTL_20__USE_DEFAULT_ATTR1__SHIFT 0x14
10054 #define SPI_PS_INPUT_CNTL_21__USE_DEFAULT_ATTR1__SHIFT 0x14
10072 #define SPI_PS_INPUT_CNTL_22__USE_DEFAULT_ATTR1__SHIFT 0x14
10090 #define SPI_PS_INPUT_CNTL_23__USE_DEFAULT_ATTR1__SHIFT 0x14
10108 #define SPI_PS_INPUT_CNTL_24__USE_DEFAULT_ATTR1__SHIFT 0x14
10126 #define SPI_PS_INPUT_CNTL_25__USE_DEFAULT_ATTR1__SHIFT 0x14
10144 #define SPI_PS_INPUT_CNTL_26__USE_DEFAULT_ATTR1__SHIFT 0x14
10162 #define SPI_PS_INPUT_CNTL_27__USE_DEFAULT_ATTR1__SHIFT 0x14
10180 #define SPI_PS_INPUT_CNTL_28__USE_DEFAULT_ATTR1__SHIFT 0x14
10198 #define SPI_PS_INPUT_CNTL_29__USE_DEFAULT_ATTR1__SHIFT 0x14
10216 #define SPI_PS_INPUT_CNTL_30__USE_DEFAULT_ATTR1__SHIFT 0x14
10234 #define SPI_PS_INPUT_CNTL_31__USE_DEFAULT_ATTR1__SHIFT 0x14
10340 #define SPI_BARYC_CNTL__POS_FLOAT_ULC__SHIFT 0x14
10368 #define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT__SHIFT 0x14
10860 #define SPI_DEBUG_CNTL__SPI_ECO_SPARE_3__SHIFT 0x14
10890 #define SPI_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
10896 #define SPI_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
10902 #define SPI_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
10908 #define SPI_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
10940 #define SPI_PERFCOUNTER_BINS__BIN2_MAX__SHIFT 0x14
11026 #define SPI_DEBUG_BUSY__PC_DEALLOC_BUSY__SHIFT 0x14
11048 #define CGTS_SM_CTRL_REG__SM_MODE_ENABLE__SHIFT 0x14
12784 #define SPI_SLAVE_DEBUG_BUSY__WAVE_WC1_BUSY__SHIFT 0x14
12876 #define SPI_SHADER_PGM_RSRC1_PS__PRIV__SHIFT 0x14
12960 #define SPI_SHADER_PGM_RSRC1_VS__PRIV__SHIFT 0x14
13048 #define SPI_SHADER_PGM_RSRC2_ES_VS__LDS_SIZE__SHIFT 0x14
13080 #define SPI_SHADER_PGM_RSRC1_GS__PRIV__SHIFT 0x14
13152 #define SPI_SHADER_PGM_RSRC2_ES_GS__LDS_SIZE__SHIFT 0x14
13174 #define SPI_SHADER_PGM_RSRC1_ES__PRIV__SHIFT 0x14
13200 #define SPI_SHADER_PGM_RSRC2_ES__LDS_SIZE__SHIFT 0x14
13272 #define SPI_SHADER_PGM_RSRC1_HS__PRIV__SHIFT 0x14
13364 #define SPI_SHADER_PGM_RSRC1_LS__PRIV__SHIFT 0x14
13522 #define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_BANKB__SHIFT 0x14
13584 #define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA3__SHIFT 0x14
13636 #define CC_SQC_BANK_DISABLE__SQC1_BANK_DISABLE__SHIFT 0x14
13644 #define USER_SQC_BANK_DISABLE__SQC1_BANK_DISABLE__SHIFT 0x14
13720 #define SQ_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14
13732 #define SQ_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14
13744 #define SQ_PERFCOUNTER2_SELECT__SPM_MODE__SHIFT 0x14
13756 #define SQ_PERFCOUNTER3_SELECT__SPM_MODE__SHIFT 0x14
13768 #define SQ_PERFCOUNTER4_SELECT__SPM_MODE__SHIFT 0x14
13780 #define SQ_PERFCOUNTER5_SELECT__SPM_MODE__SHIFT 0x14
13792 #define SQ_PERFCOUNTER6_SELECT__SPM_MODE__SHIFT 0x14
13804 #define SQ_PERFCOUNTER7_SELECT__SPM_MODE__SHIFT 0x14
13816 #define SQ_PERFCOUNTER8_SELECT__SPM_MODE__SHIFT 0x14
13828 #define SQ_PERFCOUNTER9_SELECT__SPM_MODE__SHIFT 0x14
13840 #define SQ_PERFCOUNTER10_SELECT__SPM_MODE__SHIFT 0x14
13852 #define SQ_PERFCOUNTER11_SELECT__SPM_MODE__SHIFT 0x14
13864 #define SQ_PERFCOUNTER12_SELECT__SPM_MODE__SHIFT 0x14
13876 #define SQ_PERFCOUNTER13_SELECT__SPM_MODE__SHIFT 0x14
13888 #define SQ_PERFCOUNTER14_SELECT__SPM_MODE__SHIFT 0x14
13900 #define SQ_PERFCOUNTER15_SELECT__SPM_MODE__SHIFT 0x14
14136 #define SQ_IMG_RSRC_WORD1__DATA_FORMAT__SHIFT 0x14
14162 #define SQ_IMG_RSRC_WORD3__TILING_INDEX__SHIFT 0x14
14184 #define SQ_IMG_RSRC_WORD6__LOD_HDW_CNT_EN__SHIFT 0x14
14214 #define SQ_IMG_SAMP_WORD0__FORCE_DEGAMMA__SHIFT 0x14
14238 #define SQ_IMG_SAMP_WORD2__XY_MAG_FILTER__SHIFT 0x14
14298 #define SQ_CMD__SIMD_ID__SHIFT 0x14
14336 #define SQ_WAVE_IB_DBG0__MISC_CNT__SHIFT 0x14
14398 #define SQ_WAVE_STATUS__COND_DBG_USER__SHIFT 0x14
14450 #define SQ_WAVE_HW_ID__VM_ID__SHIFT 0x14
14712 #define SQ_THREAD_TRACE_WORD_ISSUE__INST6__SHIFT 0x14
14758 #define SQC_GATCL1_CNTL__DCACHE_FORCE_IN_ORDER__SHIFT 0x14
14814 #define SQ_INTERRUPT_WORD_WAVE__CU_ID__SHIFT 0x14
14912 #define SQ_VOP_SDWA__SRC0_NEG__SHIFT 0x14
15092 #define SQ_VOP_DPP__SRC0_NEG__SHIFT 0x14
15274 #define SX_DEBUG_BUSY__POS_INMUX_VALID__SHIFT 0x14
15338 #define SX_DEBUG_BUSY_2__COL_DBIF1_FIFO_BUSY__SHIFT 0x14
15402 #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL0_BUSY__SHIFT 0x14
15466 #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL0_BUSY__SHIFT 0x14
15486 #define SX_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
15492 #define SX_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
15498 #define SX_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
15504 #define SX_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
15542 #define TCC_CTRL__WB_OR_INV_ALL_VMIDS__SHIFT 0x14
15608 #define TCC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
15618 #define TCC_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
15642 #define TCC_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
15648 #define TCC_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
15674 #define TCA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
15684 #define TCA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
15708 #define TCA_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
15714 #define TCA_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
15756 #define TD_CNTL__DISABLE_POWER_THROTTLE__SHIFT 0x14
15776 #define TD_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
15786 #define TD_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
15846 #define TA_STATUS__FA_PFIFO_EMPTYB__SHIFT 0x14
15876 #define TA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
15886 #define TA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
15968 #define TCP_CHAN_STEER_LO__CHAN5__SHIFT 0x14
15984 #define TCP_CHAN_STEER_HI__CHAND__SHIFT 0x14
16008 #define TCP_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
16018 #define TCP_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
16042 #define TCP_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
16048 #define TCP_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
16104 #define TC_CFG_L1_LOAD_POLICY0__POLICY_10__SHIFT 0x14
16136 #define TC_CFG_L1_LOAD_POLICY1__POLICY_26__SHIFT 0x14
16188 #define TC_CFG_L1_STORE_POLICY__POLICY_20__SHIFT 0x14
16232 #define TC_CFG_L2_LOAD_POLICY0__POLICY_10__SHIFT 0x14
16264 #define TC_CFG_L2_LOAD_POLICY1__POLICY_26__SHIFT 0x14
16296 #define TC_CFG_L2_STORE_POLICY0__POLICY_10__SHIFT 0x14
16328 #define TC_CFG_L2_STORE_POLICY1__POLICY_26__SHIFT 0x14
16360 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_10__SHIFT 0x14
16798 #define GDS_OA_ADDRESS__CRAWLER_TYPE__SHIFT 0x14
16828 #define GDS_DEBUG_REG0__wbuf_fifo_empty__SHIFT 0x14
16846 #define GDS_DEBUG_REG1__addr_fifo_full__SHIFT 0x14
16906 #define GDS_DEBUG_REG4__ram_read_busy__SHIFT 0x14
16944 #define GDS_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
16950 #define GDS_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
16956 #define GDS_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
16962 #define GDS_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
17216 #define GDS_GWS_RESET0__RESOURCE20_RESET__SHIFT 0x14
17280 #define GDS_GWS_RESET1__RESOURCE52_RESET__SHIFT 0x14
17356 #define GDS_OA_CGPG_RESTORE__UNUSED__SHIFT 0x14
17584 #define VGT_DMA_CONTROL__WD_SWITCH_ON_EOP__SHIFT 0x14
17682 #define VGT_GROUP_VECT_0_FMT_CNTL__Z_OFFSET__SHIFT 0x14
17698 #define VGT_GROUP_VECT_1_FMT_CNTL__Z_OFFSET__SHIFT 0x14
17746 #define VGT_GS_MODE__GS_WRITE_OPTIMIZE__SHIFT 0x14
17972 #define IA_MULTI_VGT_PARAM__WD_SWITCH_ON_EOP__SHIFT 0x14
18166 #define WD_DEBUG_REG0__se0_synced_q__SHIFT 0x14
18218 #define WD_DEBUG_REG1__free_cnt_q__SHIFT 0x14
18260 #define WD_DEBUG_REG2__p1_free_cnt_q__SHIFT 0x14
18312 #define WD_DEBUG_REG3__last_inst_of_dma_p2__SHIFT 0x14
18370 #define WD_DEBUG_REG4__rbiu_spl_pipe0_lockout__SHIFT 0x14
18432 #define WD_DEBUG_REG5__p1_last_inst_of_dma_p2__SHIFT 0x14
18474 #define WD_DEBUG_REG7__se0_thdgrp_is_event__SHIFT 0x14
18518 #define WD_DEBUG_REG8__tf_data_fifo_cnt_q__SHIFT 0x14
18558 #define WD_DEBUG_REG9__tf_pointer_p0_q__SHIFT 0x14
18708 #define IA_DEBUG_REG1__stage3_dr__SHIFT 0x14
18770 #define IA_DEBUG_REG2__hp_stage3_dr__SHIFT 0x14
18834 #define IA_DEBUG_REG3__pair0_valid_p1__SHIFT 0x14
18892 #define IA_DEBUG_REG4__di_event_flag_p1_q__SHIFT 0x14
18950 #define IA_DEBUG_REG7__num_indx_in_group_p2_q__SHIFT 0x14
19042 #define IA_DEBUG_REG9__prim_counter_q__SHIFT 0x14
19084 #define VGT_DEBUG_REG0__SPARE3__SHIFT 0x14
19148 #define VGT_DEBUG_REG1__pt_out_indx_valid__SHIFT 0x14
19212 #define VGT_DEBUG_REG2__p0_rtr__SHIFT 0x14
19326 #define VGT_DEBUG_REG8__tm_rcm_gs_tbl_rtr__SHIFT 0x14
19454 #define VGT_DEBUG_REG11__es_r0_rtr__SHIFT 0x14
19580 #define VGT_DEBUG_REG15__SPARE25__SHIFT 0x14
19624 #define VGT_DEBUG_REG16__prim_valid_r0_q__SHIFT 0x14
19688 #define VGT_DEBUG_REG18__last_group_of_instance_r0_q__SHIFT 0x14
19744 #define VGT_DEBUG_REG19__buffered_prim_type_event__SHIFT 0x14
19808 #define VGT_DEBUG_REG21__is_event_p0_q__SHIFT 0x14
19852 #define VGT_DEBUG_REG22__cm_state26__SHIFT 0x14
19936 #define VGT_DEBUG_REG26__cm_state10__SHIFT 0x14
19984 #define VGT_DEBUG_REG27__gsc_indx_count_p0_q__SHIFT 0x14
20022 #define VGT_DEBUG_REG28__last_point_of_inner_ring_p1__SHIFT 0x14
20080 #define VGT_DEBUG_REG29__last_point_of_inner_ring_p1__SHIFT 0x14
20144 #define VGT_DEBUG_REG31__pg_con_outer_point1_rts__SHIFT 0x14
20206 #define VGT_DEBUG_REG32__pg_inner2_point_fifo_full__SHIFT 0x14
20264 #define VGT_DEBUG_REG33__last_patch_of_tg_p0_q__SHIFT 0x14
20318 #define VGT_DEBUG_REG34__last_point_of_inner_ring_p1__SHIFT 0x14
20350 #define VGT_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
20360 #define VGT_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
20410 #define IA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14