dc/dml/amdgpu_dml1_display_rq_dlg_calc.c

544 		struct _vcs_dpi_display_data_rq_dlg_params_st *rq_dlg_param,
681 		rq_dlg_param->swath_width_ub = dml_round_to_multiple(vp_width - 1, blk256_width, 1)
683 		rq_dlg_param->req_per_swath_ub = rq_dlg_param->swath_width_ub >> log2_blk256_width;
685 		rq_dlg_param->swath_width_ub = dml_round_to_multiple(
689 		rq_dlg_param->req_per_swath_ub = rq_dlg_param->swath_width_ub >> log2_blk256_height;
693 		rq_misc_param->full_swath_bytes = rq_dlg_param->swath_width_ub * blk256_height
696 		rq_misc_param->full_swath_bytes = rq_dlg_param->swath_width_ub * blk256_width
725 		rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_width;
730 		rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_height;
732 	rq_dlg_param->meta_bytes_per_row_ub = rq_dlg_param->meta_req_per_row_ub * 64;
760 	rq_dlg_param->meta_pte_bytes_per_frame_ub = meta_pte_bytes_per_frame_ub;
774 		rq_dlg_param->meta_chunks_per_row_ub = meta_chunk_per_row_int + 1;
776 		rq_dlg_param->meta_chunks_per_row_ub = meta_chunk_per_row_int + 2;
778 	rq_dlg_param->meta_row_height = 1 << log2_meta_row_height;
846 		rq_dlg_param->dpte_row_height = 1 << log2_dpte_row_height;
855 		rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width;
862 			rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width;
869 			rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_height;
871 		rq_dlg_param->dpte_row_height = 1 << log2_dpte_row_height;
873 	rq_dlg_param->dpte_bytes_per_row_ub = rq_dlg_param->dpte_req_per_row_ub * 64;
883 		rq_dlg_param->dpte_row_height = 1 << log2_dpte_row_height;
910 	rq_dlg_param->dpte_groups_per_row_ub = dml_ceil(
930 	if (rq_dlg_param->meta_row_height != func_meta_row_height) {
932 				"MISMATCH: rq_dlg_param->meta_row_height = %d",
933 				rq_dlg_param->meta_row_height);
938 	if (rq_dlg_param->dpte_row_height != func_dpte_row_height) {
940 				"MISMATCH: rq_dlg_param->dpte_row_height = %d",
941 				rq_dlg_param->dpte_row_height);
988 		const struct _vcs_dpi_display_rq_dlg_params_st rq_dlg_param,
1217 	swath_height_l = rq_dlg_param.rq_l.swath_height;
1218 	swath_width_ub_l = rq_dlg_param.rq_l.swath_width_ub;
1219 	dpte_bytes_per_row_ub_l = rq_dlg_param.rq_l.dpte_bytes_per_row_ub;
1220 	dpte_groups_per_row_ub_l = rq_dlg_param.rq_l.dpte_groups_per_row_ub;
1221 	meta_pte_bytes_per_frame_ub_l = rq_dlg_param.rq_l.meta_pte_bytes_per_frame_ub;
1222 	meta_bytes_per_row_ub_l = rq_dlg_param.rq_l.meta_bytes_per_row_ub;
1224 	swath_height_c = rq_dlg_param.rq_c.swath_height;
1225 	swath_width_ub_c = rq_dlg_param.rq_c.swath_width_ub;
1226 	dpte_bytes_per_row_ub_c = rq_dlg_param.rq_c.dpte_bytes_per_row_ub;
1227 	dpte_groups_per_row_ub_c = rq_dlg_param.rq_c.dpte_groups_per_row_ub;
1229 	meta_chunks_per_row_ub_l = rq_dlg_param.rq_l.meta_chunks_per_row_ub;
1540 	req_per_swath_ub_l = rq_dlg_param.rq_l.req_per_swath_ub;
1541 	req_per_swath_ub_c = rq_dlg_param.rq_c.req_per_swath_ub;
1542 	meta_row_height_l = rq_dlg_param.rq_l.meta_row_height;
1547 	dpte_row_height_l = rq_dlg_param.rq_l.dpte_row_height;
1548 	dpte_row_height_c = rq_dlg_param.rq_c.dpte_row_height;