dc/dcn20/dcn20_dwb.h

55 #define SF(reg_name, field_name, post_fix)\
108 	SF(WB_ENABLE, WB_ENABLE, mask_sh),\
109 	SF(WB_EC_CONFIG, DISPCLK_R_WB_GATE_DIS, mask_sh),\
110 	SF(WB_EC_CONFIG, DISPCLK_G_WB_GATE_DIS, mask_sh),\
111 	SF(WB_EC_CONFIG, DISPCLK_G_WBSCL_GATE_DIS, mask_sh),\
112 	SF(WB_EC_CONFIG, WB_TEST_CLK_SEL, mask_sh),\
113 	SF(WB_EC_CONFIG, WB_LB_LS_DIS, mask_sh),\
114 	SF(WB_EC_CONFIG, WB_LB_SD_DIS, mask_sh),\
115 	SF(WB_EC_CONFIG, WB_LUT_LS_DIS, mask_sh),\
116 	SF(WB_EC_CONFIG, WBSCL_LB_MEM_PWR_MODE_SEL, mask_sh),\
117 	SF(WB_EC_CONFIG, WBSCL_LB_MEM_PWR_DIS, mask_sh),\
118 	SF(WB_EC_CONFIG, WBSCL_LB_MEM_PWR_FORCE, mask_sh),\
119 	SF(WB_EC_CONFIG, WBSCL_LB_MEM_PWR_STATE, mask_sh),\
120 	SF(WB_EC_CONFIG, WB_RAM_PW_SAVE_MODE, mask_sh),\
121 	SF(WB_EC_CONFIG, WBSCL_LUT_MEM_PWR_STATE, mask_sh),\
122 	SF(CNV_MODE, CNV_OUT_BPC, mask_sh),\
123 	SF(CNV_MODE, CNV_FRAME_CAPTURE_RATE, mask_sh),\
124 	SF(CNV_MODE, CNV_WINDOW_CROP_EN, mask_sh),\
125 	SF(CNV_MODE, CNV_STEREO_TYPE, mask_sh),\
126 	SF(CNV_MODE, CNV_INTERLACED_MODE, mask_sh),\
127 	SF(CNV_MODE, CNV_EYE_SELECTION, mask_sh),\
128 	SF(CNV_MODE, CNV_STEREO_POLARITY, mask_sh),\
129 	SF(CNV_MODE, CNV_INTERLACED_FIELD_ORDER, mask_sh),\
130 	SF(CNV_MODE, CNV_STEREO_SPLIT, mask_sh),\
131 	SF(CNV_MODE, CNV_NEW_CONTENT, mask_sh),\
132 	SF(CNV_MODE, CNV_FRAME_CAPTURE_EN_CURRENT, mask_sh),\
133 	SF(CNV_MODE, CNV_FRAME_CAPTURE_EN, mask_sh),\
134 	SF(CNV_WINDOW_START, CNV_WINDOW_START_X, mask_sh),\
135 	SF(CNV_WINDOW_START, CNV_WINDOW_START_Y, mask_sh),\
136 	SF(CNV_WINDOW_SIZE, CNV_WINDOW_WIDTH, mask_sh),\
137 	SF(CNV_WINDOW_SIZE, CNV_WINDOW_HEIGHT, mask_sh),\
138 	SF(CNV_UPDATE, CNV_UPDATE_PENDING, mask_sh),\
139 	SF(CNV_UPDATE, CNV_UPDATE_TAKEN, mask_sh),\
140 	SF(CNV_UPDATE, CNV_UPDATE_LOCK, mask_sh),\
141 	SF(CNV_SOURCE_SIZE, CNV_SOURCE_WIDTH, mask_sh),\
142 	SF(CNV_SOURCE_SIZE, CNV_SOURCE_HEIGHT, mask_sh),\
143 	SF(CNV_TEST_CNTL, CNV_TEST_CRC_EN, mask_sh),\
144 	SF(CNV_TEST_CNTL, CNV_TEST_CRC_CONT_EN, mask_sh),\
145 	SF(CNV_TEST_CRC_RED, CNV_TEST_CRC_RED_MASK, mask_sh),\
146 	SF(CNV_TEST_CRC_RED, CNV_TEST_CRC_SIG_RED, mask_sh),\
147 	SF(CNV_TEST_CRC_GREEN, CNV_TEST_CRC_GREEN_MASK, mask_sh),\
148 	SF(CNV_TEST_CRC_GREEN, CNV_TEST_CRC_SIG_GREEN, mask_sh),\
149 	SF(CNV_TEST_CRC_BLUE, CNV_TEST_CRC_BLUE_MASK, mask_sh),\
150 	SF(CNV_TEST_CRC_BLUE, CNV_TEST_CRC_SIG_BLUE, mask_sh),\
151 	SF(WB_DEBUG_CTRL, WB_DEBUG_EN, mask_sh),\
152 	SF(WB_DEBUG_CTRL, WB_DEBUG_SEL, mask_sh),\
153 	SF(WB_DBG_MODE, WB_DBG_MODE_EN, mask_sh),\
154 	SF(WB_DBG_MODE, WB_DBG_DIN_FMT, mask_sh),\
155 	SF(WB_DBG_MODE, WB_DBG_36MODE, mask_sh),\
156 	SF(WB_DBG_MODE, WB_DBG_CMAP, mask_sh),\
157 	SF(WB_DBG_MODE, WB_DBG_PXLRATE_ERROR, mask_sh),\
158 	SF(WB_DBG_MODE, WB_DBG_SOURCE_WIDTH, mask_sh),\
159 	SF(WB_HW_DEBUG, WB_HW_DEBUG, mask_sh),\
160 	SF(WB_SOFT_RESET, WB_SOFT_RESET, mask_sh),\
161 	SF(CNV_TEST_DEBUG_INDEX, CNV_TEST_DEBUG_INDEX, mask_sh),\
162 	SF(CNV_TEST_DEBUG_INDEX, CNV_TEST_DEBUG_WRITE_EN, mask_sh),\
163 	SF(CNV_TEST_DEBUG_DATA, CNV_TEST_DEBUG_DATA, mask_sh),\
164 	SF(WBSCL_COEF_RAM_SELECT, WBSCL_COEF_RAM_TAP_PAIR_IDX, mask_sh),\
165 	SF(WBSCL_COEF_RAM_SELECT, WBSCL_COEF_RAM_PHASE, mask_sh),\
166 	SF(WBSCL_COEF_RAM_SELECT, WBSCL_COEF_RAM_FILTER_TYPE, mask_sh),\
167 	SF(WBSCL_COEF_RAM_TAP_DATA, WBSCL_COEF_RAM_EVEN_TAP_COEF, mask_sh),\
168 	SF(WBSCL_COEF_RAM_TAP_DATA, WBSCL_COEF_RAM_EVEN_TAP_COEF_EN, mask_sh),\
169 	SF(WBSCL_COEF_RAM_TAP_DATA, WBSCL_COEF_RAM_ODD_TAP_COEF, mask_sh),\
170 	SF(WBSCL_COEF_RAM_TAP_DATA, WBSCL_COEF_RAM_ODD_TAP_COEF_EN, mask_sh),\
171 	SF(WBSCL_MODE, WBSCL_MODE, mask_sh),\
172 	SF(WBSCL_MODE, WBSCL_OUT_BIT_DEPTH, mask_sh),\
173 	SF(WBSCL_TAP_CONTROL, WBSCL_V_NUM_OF_TAPS_Y_RGB, mask_sh),\
174 	SF(WBSCL_TAP_CONTROL, WBSCL_V_NUM_OF_TAPS_CBCR, mask_sh),\
175 	SF(WBSCL_TAP_CONTROL, WBSCL_H_NUM_OF_TAPS_Y_RGB, mask_sh),\
176 	SF(WBSCL_TAP_CONTROL, WBSCL_H_NUM_OF_TAPS_CBCR, mask_sh),\
177 	SF(WBSCL_DEST_SIZE, WBSCL_DEST_HEIGHT, mask_sh),\
178 	SF(WBSCL_DEST_SIZE, WBSCL_DEST_WIDTH, mask_sh),\
179 	SF(WBSCL_HORZ_FILTER_SCALE_RATIO, WBSCL_H_SCALE_RATIO, mask_sh),\
180 	SF(WBSCL_HORZ_FILTER_INIT_Y_RGB, WBSCL_H_INIT_FRAC_Y_RGB, mask_sh),\
181 	SF(WBSCL_HORZ_FILTER_INIT_Y_RGB, WBSCL_H_INIT_INT_Y_RGB, mask_sh),\
182 	SF(WBSCL_HORZ_FILTER_INIT_CBCR, WBSCL_H_INIT_FRAC_CBCR, mask_sh),\
183 	SF(WBSCL_HORZ_FILTER_INIT_CBCR, WBSCL_H_INIT_INT_CBCR, mask_sh),\
184 	SF(WBSCL_VERT_FILTER_SCALE_RATIO, WBSCL_V_SCALE_RATIO, mask_sh),\
185 	SF(WBSCL_VERT_FILTER_INIT_Y_RGB, WBSCL_V_INIT_FRAC_Y_RGB, mask_sh),\
186 	SF(WBSCL_VERT_FILTER_INIT_Y_RGB, WBSCL_V_INIT_INT_Y_RGB, mask_sh),\
187 	SF(WBSCL_VERT_FILTER_INIT_CBCR, WBSCL_V_INIT_FRAC_CBCR, mask_sh),\
188 	SF(WBSCL_VERT_FILTER_INIT_CBCR, WBSCL_V_INIT_INT_CBCR, mask_sh),\
189 	SF(WBSCL_ROUND_OFFSET, WBSCL_ROUND_OFFSET_Y_RGB, mask_sh),\
190 	SF(WBSCL_ROUND_OFFSET, WBSCL_ROUND_OFFSET_CBCR, mask_sh),\
191 	SF(WBSCL_OVERFLOW_STATUS, WBSCL_DATA_OVERFLOW_FLAG, mask_sh),\
192 	SF(WBSCL_OVERFLOW_STATUS, WBSCL_DATA_OVERFLOW_ACK, mask_sh),\
193 	SF(WBSCL_OVERFLOW_STATUS, WBSCL_DATA_OVERFLOW_MASK, mask_sh),\
194 	SF(WBSCL_OVERFLOW_STATUS, WBSCL_DATA_OVERFLOW_INT_STATUS, mask_sh),\
195 	SF(WBSCL_OVERFLOW_STATUS, WBSCL_DATA_OVERFLOW_INT_TYPE, mask_sh),\
196 	SF(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL_HOST_CONFLICT_FLAG, mask_sh),\
197 	SF(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL_HOST_CONFLICT_ACK, mask_sh),\
198 	SF(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL_HOST_CONFLICT_MASK, mask_sh),\
199 	SF(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL_HOST_CONFLICT_INT_STATUS, mask_sh),\
200 	SF(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL_HOST_CONFLICT_INT_TYPE, mask_sh),\
201 	SF(WBSCL_TEST_CNTL, WBSCL_TEST_CRC_EN, mask_sh),\
202 	SF(WBSCL_TEST_CNTL, WBSCL_TEST_CRC_CONT_EN, mask_sh),\
203 	SF(WBSCL_TEST_CRC_RED, WBSCL_TEST_CRC_RED_MASK, mask_sh),\
204 	SF(WBSCL_TEST_CRC_RED, WBSCL_TEST_CRC_SIG_RED, mask_sh),\
205 	SF(WBSCL_TEST_CRC_GREEN, WBSCL_TEST_CRC_GREEN_MASK, mask_sh),\
206 	SF(WBSCL_TEST_CRC_GREEN, WBSCL_TEST_CRC_SIG_GREEN, mask_sh),\
207 	SF(WBSCL_TEST_CRC_BLUE, WBSCL_TEST_CRC_BLUE_MASK, mask_sh),\
208 	SF(WBSCL_TEST_CRC_BLUE, WBSCL_TEST_CRC_SIG_BLUE, mask_sh),\
209 	SF(WBSCL_BACKPRESSURE_CNT_EN, WBSCL_BACKPRESSURE_CNT_EN, mask_sh),\
210 	SF(WB_MCIF_BACKPRESSURE_CNT, WB_MCIF_Y_MAX_BACKPRESSURE, mask_sh),\
211 	SF(WB_MCIF_BACKPRESSURE_CNT, WB_MCIF_C_MAX_BACKPRESSURE, mask_sh),\
212 	SF(WBSCL_CLAMP_Y_RGB, WBSCL_CLAMP_UPPER_Y_RGB, mask_sh),\
213 	SF(WBSCL_CLAMP_Y_RGB, WBSCL_CLAMP_LOWER_Y_RGB, mask_sh),\
214 	SF(WBSCL_CLAMP_CBCR, WBSCL_CLAMP_UPPER_CBCR, mask_sh),\
215 	SF(WBSCL_CLAMP_CBCR, WBSCL_CLAMP_LOWER_CBCR, mask_sh),\
216 	SF(WBSCL_OUTSIDE_PIX_STRATEGY, WBSCL_OUTSIDE_PIX_STRATEGY, mask_sh),\
217 	SF(WBSCL_OUTSIDE_PIX_STRATEGY, WBSCL_BLACK_COLOR_G_Y, mask_sh),\
218 	SF(WBSCL_OUTSIDE_PIX_STRATEGY_CBCR, WBSCL_BLACK_COLOR_B_CB, mask_sh),\
219 	SF(WBSCL_OUTSIDE_PIX_STRATEGY_CBCR, WBSCL_BLACK_COLOR_R_CR, mask_sh),\
220 	SF(WBSCL_DEBUG, WBSCL_DEBUG, mask_sh),\
221 	SF(WBSCL_TEST_DEBUG_INDEX, WBSCL_TEST_DEBUG_INDEX, mask_sh),\
222 	SF(WBSCL_TEST_DEBUG_INDEX, WBSCL_TEST_DEBUG_WRITE_EN, mask_sh),\
223 	SF(WBSCL_TEST_DEBUG_DATA, WBSCL_TEST_DEBUG_DATA, mask_sh),\
224 	SF(WB_WARM_UP_MODE_CTL1, WIDTH_WARMUP, mask_sh),\
225 	SF(WB_WARM_UP_MODE_CTL1, HEIGHT_WARMUP, mask_sh),\
226 	SF(WB_WARM_UP_MODE_CTL1, GMC_WARM_UP_ENABLE, mask_sh),\
227 	SF(WB_WARM_UP_MODE_CTL2, DATA_VALUE_WARMUP, mask_sh),\
228 	SF(WB_WARM_UP_MODE_CTL2, MODE_WARMUP, mask_sh),\
229 	SF(WB_WARM_UP_MODE_CTL2, DATA_DEPTH_WARMUP, mask_sh)