Lines Matching refs:pipes
1601 /* The number of DSCs can be less than the number of pipes */
1833 struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes)
1844 pipes[pipe_cnt].dout.wb_enable = (wb_info->wb_enabled == true) ? 1 : 0;
1845 pipes[pipe_cnt].dout.num_active_wb++;
1846 pipes[pipe_cnt].dout.wb.wb_src_height = wb_info->dwb_params.cnv_params.crop_height;
1847 pipes[pipe_cnt].dout.wb.wb_src_width = wb_info->dwb_params.cnv_params.crop_width;
1848 pipes[pipe_cnt].dout.wb.wb_dst_width = wb_info->dwb_params.dest_width;
1849 pipes[pipe_cnt].dout.wb.wb_dst_height = wb_info->dwb_params.dest_height;
1850 pipes[pipe_cnt].dout.wb.wb_htaps_luma = 1;
1851 pipes[pipe_cnt].dout.wb.wb_vtaps_luma = 1;
1852 pipes[pipe_cnt].dout.wb.wb_htaps_chroma = wb_info->dwb_params.scaler_taps.h_taps_c;
1853 pipes[pipe_cnt].dout.wb.wb_vtaps_chroma = wb_info->dwb_params.scaler_taps.v_taps_c;
1854 pipes[pipe_cnt].dout.wb.wb_hratio = 1.0;
1855 pipes[pipe_cnt].dout.wb.wb_vratio = 1.0;
1858 pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_420_8;
1860 pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_420_10;
1862 pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_444_32;
1886 struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes)
1920 pipes[pipe_cnt].pipe.src.dynamic_metadata_enable = 0;
1921 pipes[pipe_cnt].pipe.src.dcc = 0;
1922 pipes[pipe_cnt].pipe.src.vm = 0;*/
1924 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
1926 pipes[pipe_cnt].dout.dsc_enable = res_ctx->pipe_ctx[i].stream->timing.flags.DSC;
1928 pipes[pipe_cnt].dout.dsc_slices = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.num_slices_h;
1930 pipes[pipe_cnt].pipe.src.dynamic_metadata_enable = true;
1932 pipes[pipe_cnt].pipe.src.dynamic_metadata_lines_before_active =
1936 pipes[pipe_cnt].pipe.src.dynamic_metadata_xmit_bytes =
1939 pipes[pipe_cnt].pipe.src.dcc = false;
1940 pipes[pipe_cnt].pipe.src.dcc_rate = 1;
1941 pipes[pipe_cnt].pipe.dest.synchronized_vblank_all_planes = synchronized_vblank;
1942 pipes[pipe_cnt].pipe.dest.hblank_start = timing->h_total - timing->h_front_porch;
1943 pipes[pipe_cnt].pipe.dest.hblank_end = pipes[pipe_cnt].pipe.dest.hblank_start
1947 pipes[pipe_cnt].pipe.dest.vblank_start = v_total - front_porch;
1948 pipes[pipe_cnt].pipe.dest.vblank_end = pipes[pipe_cnt].pipe.dest.vblank_start
1952 pipes[pipe_cnt].pipe.dest.htotal = timing->h_total;
1953 pipes[pipe_cnt].pipe.dest.vtotal = v_total;
1954 pipes[pipe_cnt].pipe.dest.hactive = timing->h_addressable;
1955 pipes[pipe_cnt].pipe.dest.vactive = timing->v_addressable;
1956 pipes[pipe_cnt].pipe.dest.interlaced = timing->flags.INTERLACE;
1957 pipes[pipe_cnt].pipe.dest.pixel_rate_mhz = timing->pix_clk_100hz/10000.0;
1959 pipes[pipe_cnt].pipe.dest.pixel_rate_mhz *= 2;
1960 pipes[pipe_cnt].pipe.dest.otg_inst = res_ctx->pipe_ctx[i].stream_res.tg->inst;
1961 pipes[pipe_cnt].dout.dp_lanes = 4;
1962 pipes[pipe_cnt].pipe.dest.vtotal_min = res_ctx->pipe_ctx[i].stream->adjust.v_total_min;
1963 pipes[pipe_cnt].pipe.dest.vtotal_max = res_ctx->pipe_ctx[i].stream->adjust.v_total_max;
1966 pipes[pipe_cnt].pipe.dest.odm_combine = dm_odm_combine_mode_2to1;
1969 pipes[pipe_cnt].pipe.dest.odm_combine = dm_odm_combine_mode_disabled;
1971 pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx;
1974 pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].top_pipe->pipe_idx;
1980 pipes[pipe_cnt].pipe.src.hsplit_grp = first_pipe->pipe_idx;
1986 pipes[pipe_cnt].dout.output_type = dm_dp;
1989 pipes[pipe_cnt].dout.output_type = dm_edp;
1994 pipes[pipe_cnt].dout.output_type = dm_hdmi;
1998 pipes[pipe_cnt].dout.output_type = dm_dp;
1999 pipes[pipe_cnt].dout.dp_lanes = 4;
2035 pipes[pipe_cnt].dout.output_format = dm_444;
2036 pipes[pipe_cnt].dout.output_bpp = output_bpc * 3;
2039 pipes[pipe_cnt].dout.output_format = dm_420;
2040 pipes[pipe_cnt].dout.output_bpp = (output_bpc * 3.0) / 2;
2044 pipes[pipe_cnt].dout.output_format = dm_s422;
2046 pipes[pipe_cnt].dout.output_format = dm_n422;
2047 pipes[pipe_cnt].dout.output_bpp = output_bpc * 2;
2050 pipes[pipe_cnt].dout.output_format = dm_444;
2051 pipes[pipe_cnt].dout.output_bpp = output_bpc * 3;
2055 pipes[pipe_cnt].dout.output_bpp = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.bits_per_pixel / 16.0;
2058 pipes[pipe_cnt].dout.output_bpc = 12;
2063 pipes[pipe_cnt].pipe.src.num_cursors = 2;
2064 pipes[pipe_cnt].pipe.src.cur0_src_width = 256;
2065 pipes[pipe_cnt].pipe.src.cur0_bpp = dm_cur_32bit;
2066 pipes[pipe_cnt].pipe.src.cur1_src_width = 256;
2067 pipes[pipe_cnt].pipe.src.cur1_bpp = dm_cur_32bit;
2070 pipes[pipe_cnt].pipe.src.source_scan = dm_horz;
2071 pipes[pipe_cnt].pipe.src.sw_mode = dm_sw_linear;
2072 pipes[pipe_cnt].pipe.src.macro_tile_size = dm_64k_tile;
2073 pipes[pipe_cnt].pipe.src.viewport_width = timing->h_addressable;
2074 if (pipes[pipe_cnt].pipe.src.viewport_width > 1920)
2075 pipes[pipe_cnt].pipe.src.viewport_width = 1920;
2076 pipes[pipe_cnt].pipe.src.viewport_height = timing->v_addressable;
2077 if (pipes[pipe_cnt].pipe.src.viewport_height > 1080)
2078 pipes[pipe_cnt].pipe.src.viewport_height = 1080;
2079 pipes[pipe_cnt].pipe.src.surface_height_y = pipes[pipe_cnt].pipe.src.viewport_height;
2080 pipes[pipe_cnt].pipe.src.surface_width_y = pipes[pipe_cnt].pipe.src.viewport_width;
2081 pipes[pipe_cnt].pipe.src.surface_height_c = pipes[pipe_cnt].pipe.src.viewport_height;
2082 pipes[pipe_cnt].pipe.src.surface_width_c = pipes[pipe_cnt].pipe.src.viewport_width;
2083 pipes[pipe_cnt].pipe.src.data_pitch = ((pipes[pipe_cnt].pipe.src.viewport_width + 63) / 64) * 64; /* linear sw only */
2084 pipes[pipe_cnt].pipe.src.source_format = dm_444_32;
2085 pipes[pipe_cnt].pipe.dest.recout_width = pipes[pipe_cnt].pipe.src.viewport_width; /*vp_width/hratio*/
2086 pipes[pipe_cnt].pipe.dest.recout_height = pipes[pipe_cnt].pipe.src.viewport_height; /*vp_height/vratio*/
2087 pipes[pipe_cnt].pipe.dest.full_recout_width = pipes[pipe_cnt].pipe.dest.recout_width; /*when is_hsplit != 1*/
2088 pipes[pipe_cnt].pipe.dest.full_recout_height = pipes[pipe_cnt].pipe.dest.recout_height; /*when is_hsplit != 1*/
2089 pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_16;
2090 pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio = 1.0;
2091 pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio = 1.0;
2092 pipes[pipe_cnt].pipe.scale_ratio_depth.scl_enable = 0; /*Lb only or Full scl*/
2093 pipes[pipe_cnt].pipe.scale_taps.htaps = 1;
2094 pipes[pipe_cnt].pipe.scale_taps.vtaps = 1;
2095 pipes[pipe_cnt].pipe.src.is_hsplit = 0;
2096 pipes[pipe_cnt].pipe.dest.odm_combine = 0;
2097 pipes[pipe_cnt].pipe.dest.vtotal_min = v_total;
2098 pipes[pipe_cnt].pipe.dest.vtotal_max = v_total;
2103 pipes[pipe_cnt].pipe.src.immediate_flip = pln->flip_immediate;
2104 pipes[pipe_cnt].pipe.src.is_hsplit = (res_ctx->pipe_ctx[i].bottom_pipe
2108 pipes[pipe_cnt].pipe.src.source_scan = pln->rotation == ROTATION_ANGLE_90
2110 pipes[pipe_cnt].pipe.src.viewport_y_y = scl->viewport.y;
2111 pipes[pipe_cnt].pipe.src.viewport_y_c = scl->viewport_c.y;
2112 pipes[pipe_cnt].pipe.src.viewport_width = scl->viewport.width;
2113 pipes[pipe_cnt].pipe.src.viewport_width_c = scl->viewport_c.width;
2114 pipes[pipe_cnt].pipe.src.viewport_height = scl->viewport.height;
2115 pipes[pipe_cnt].pipe.src.viewport_height_c = scl->viewport_c.height;
2116 pipes[pipe_cnt].pipe.src.surface_width_y = pln->plane_size.surface_size.width;
2117 pipes[pipe_cnt].pipe.src.surface_height_y = pln->plane_size.surface_size.height;
2118 pipes[pipe_cnt].pipe.src.surface_width_c = pln->plane_size.chroma_size.width;
2119 pipes[pipe_cnt].pipe.src.surface_height_c = pln->plane_size.chroma_size.height;
2121 pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.surface_pitch;
2122 pipes[pipe_cnt].pipe.src.data_pitch_c = pln->plane_size.chroma_pitch;
2123 pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.meta_pitch;
2124 pipes[pipe_cnt].pipe.src.meta_pitch_c = pln->dcc.meta_pitch_c;
2126 pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.surface_pitch;
2127 pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.meta_pitch;
2129 pipes[pipe_cnt].pipe.src.dcc = pln->dcc.enable;
2130 pipes[pipe_cnt].pipe.dest.recout_width = scl->recout.width;
2131 pipes[pipe_cnt].pipe.dest.recout_height = scl->recout.height;
2132 pipes[pipe_cnt].pipe.dest.full_recout_width = scl->recout.width;
2133 pipes[pipe_cnt].pipe.dest.full_recout_height = scl->recout.height;
2135 pipes[pipe_cnt].pipe.dest.full_recout_width +=
2137 pipes[pipe_cnt].pipe.dest.full_recout_height +=
2140 pipes[pipe_cnt].pipe.dest.full_recout_width +=
2142 pipes[pipe_cnt].pipe.dest.full_recout_height +=
2146 pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_16;
2147 pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio = (double) scl->ratios.horz.value / (1ULL<<32);
2148 pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio_c = (double) scl->ratios.horz_c.value / (1ULL<<32);
2149 pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio = (double) scl->ratios.vert.value / (1ULL<<32);
2150 pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio_c = (double) scl->ratios.vert_c.value / (1ULL<<32);
2151 pipes[pipe_cnt].pipe.scale_ratio_depth.scl_enable =
2157 pipes[pipe_cnt].pipe.scale_taps.htaps = scl->taps.h_taps;
2158 pipes[pipe_cnt].pipe.scale_taps.htaps_c = scl->taps.h_taps_c;
2159 pipes[pipe_cnt].pipe.scale_taps.vtaps = scl->taps.v_taps;
2160 pipes[pipe_cnt].pipe.scale_taps.vtaps_c = scl->taps.v_taps_c;
2162 pipes[pipe_cnt].pipe.src.macro_tile_size =
2165 &pipes[pipe_cnt].pipe.src.sw_mode);
2170 pipes[pipe_cnt].pipe.src.source_format = dm_420_8;
2174 pipes[pipe_cnt].pipe.src.source_format = dm_420_10;
2179 pipes[pipe_cnt].pipe.src.source_format = dm_444_64;
2183 pipes[pipe_cnt].pipe.src.source_format = dm_444_16;
2186 pipes[pipe_cnt].pipe.src.source_format = dm_444_8;
2189 pipes[pipe_cnt].pipe.src.source_format = dm_444_32;
2198 dc->res_pool->funcs->populate_dml_writeback_from_context(dc, res_ctx, pipes);
2235 display_e2e_pipe_params_st *pipes,
2265 wb_arb_params->cli_watermark[k] = get_wm_writeback_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2266 wb_arb_params->pstate_watermark[k] = get_wm_writeback_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2334 * Same logic applies for ODM pipes. Since mpo is not allowed with odm
2402 /* merge previously split odm pipes since mode support needs to make the decision */
2431 /* merge previously mpc split pipes since mode support needs to make the decision */
2496 /* Avoid split loop looks for lowest voltage level that allows most unsplit pipes possible */
2549 display_e2e_pipe_params_st *pipes,
2558 ASSERT(pipes);
2559 if (!pipes)
2564 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes);
2573 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
2662 display_e2e_pipe_params_st *pipes,
2673 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
2674 pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
2677 pipes[pipe_cnt].clks_cfg.dppclk_mhz =
2680 pipes[pipe_cnt].pipe.dest.odm_combine =
2683 pipes[pipe_cnt].pipe.dest.odm_combine = 0;
2686 pipes[pipe_cnt].clks_cfg.dppclk_mhz =
2689 pipes[pipe_cnt].pipe.dest.odm_combine =
2692 pipes[pipe_cnt].pipe.dest.odm_combine = 0;
2696 pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz;
2697 pipes[pipe_cnt].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz;
2699 if (dc->debug.min_disp_clk_khz > pipes[pipe_cnt].clks_cfg.dispclk_mhz * 1000)
2700 pipes[pipe_cnt].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0;
2701 if (dc->debug.min_dpp_clk_khz > pipes[pipe_cnt].clks_cfg.dppclk_mhz * 1000)
2702 pipes[pipe_cnt].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0;
2710 context, pipes);
2713 context, pipes);
2718 pipes[0].clks_cfg.voltage = vlevel;
2719 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz;
2720 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
2724 pipes[0].clks_cfg.voltage = 1;
2725 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].dcfclk_mhz;
2726 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].socclk_mhz;
2728 context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2729 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2730 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2731 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2732 context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2733 context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2734 context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2735 context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2738 pipes[0].clks_cfg.voltage = 2;
2739 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz;
2740 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz;
2742 context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2743 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2744 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2745 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2746 context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2747 context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2748 context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2751 pipes[0].clks_cfg.voltage = 3;
2752 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz;
2753 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz;
2755 context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2756 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2757 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2758 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2759 context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2760 context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2761 context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2763 pipes[0].clks_cfg.voltage = vlevel;
2764 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz;
2765 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
2766 context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2767 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2768 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2769 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2770 context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2771 context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2772 context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2777 display_e2e_pipe_params_st *pipes,
2785 dc->res_pool->funcs->set_mcif_arb_params(dc, context, pipes, pipe_cnt);
2799 * An artifact of dml pipe split/odm is that pipes get merged back together for
2808 display_pipe_source_params_st *src = &pipes[pipe_idx].pipe.src;
2809 display_pipe_dest_params_st *dst = &pipes[pipe_idx].pipe.dest;
2816 * j iterates inside pipes array, unlike i which iterates inside
2821 display_pipe_source_params_st *src_j = &pipes[j].pipe.src;
2822 display_pipe_dest_params_st *dst_j = &pipes[j].pipe.dest;
2842 if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)
2843 context->bw_ctx.bw.dcn.clk.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
2845 pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
2847 context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest;
2865 pipes,
2874 pipes[pipe_idx].pipe);
2889 display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL);
2894 out = dcn20_fast_validate_bw(dc, context, pipes, &pipe_cnt, pipe_split_from, &vlevel);
2909 dcn20_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel);
2910 dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
2924 kfree(pipes);