Lines Matching refs:num_states
302 .num_states = 5,
2502 for (vlevel_split = vlevel; vlevel <= context->bw_ctx.dml.soc.num_states; vlevel++)
2506 if (vlevel > context->bw_ctx.dml.soc.num_states)
2575 if (vlevel > context->bw_ctx.dml.soc.num_states)
2643 context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] =
2918 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
3147 for (i = 0; i < bb->num_states; i++) {
3182 for (i = bb->num_states - 1; i > 1; i--) {
3203 bb->num_states--;
3208 struct pp_smu_nv_clock_table *max_clocks, unsigned int *uclk_states, unsigned int num_states)
3215 if (num_states == 0)
3231 for (i = 0; i < num_states; i++) {
3262 bb->num_states = num_calculated_states;
3266 bb->clock_limits[num_calculated_states].state = bb->num_states;
3420 dcn2_0_nv12_soc.num_states =
3421 le32_to_cpu(bb->num_states);
3423 for (i = 0; i < dcn2_0_nv12_soc.num_states; i++) {
3448 unsigned int num_states = 0;
3455 (&pool->base.pp_smu->nv_funcs.pp_smu, uclk_states, &num_states);
3470 if (clock_limits_available && uclk_states_available && num_states)
3471 dcn20_update_bounding_box(dc, loaded_bb, &max_clocks, uclk_states, num_states);
3632 if (loaded_bb->num_states == 1) {
3640 } else if (loaded_bb->num_states > 1) {
3641 for (i = 0; i < 4 && i < loaded_bb->num_states; i++) {