dc/dcn10/amdgpu_dcn10_dpp_dscl.c

238 static const uint16_t *dpp1_dscl_get_filter_coeffs_64p(int taps, struct fixed31_32 ratio)
240 	if (taps == 8)
242 	else if (taps == 7)
244 	else if (taps == 6)
246 	else if (taps == 5)
248 	else if (taps == 4)
250 	else if (taps == 3)
252 	else if (taps == 2)
254 	else if (taps == 1)
265 		uint32_t taps,
269 	const int tap_pairs = (taps + 1) / 2;
281 			even_coef = filter[phase * taps + 2 * pair];
282 			if ((pair * 2 + 1) < taps)
283 				odd_coef = filter[phase * taps + 2 * pair + 1];
318 	h_2tap_hardcode_coef_en = scl_data->taps.h_taps < 3
319 					&& scl_data->taps.h_taps_c < 3
320 		&& (scl_data->taps.h_taps > 1 && scl_data->taps.h_taps_c > 1);
321 	v_2tap_hardcode_coef_en = scl_data->taps.v_taps < 3
322 					&& scl_data->taps.v_taps_c < 3
323 		&& (scl_data->taps.v_taps > 1 && scl_data->taps.v_taps_c > 1);
340 				scl_data->taps.h_taps, scl_data->ratios.horz);
342 				scl_data->taps.v_taps, scl_data->ratios.vert);
349 					scl_data->taps.h_taps_c, scl_data->ratios.horz_c);
351 					scl_data->taps.v_taps_c, scl_data->ratios.vert_c);
361 					dpp, scl_data->taps.h_taps,
367 					dpp, scl_data->taps.v_taps,
374 						dpp, scl_data->taps.h_taps_c,
379 						dpp, scl_data->taps.v_taps_c,
486 	int vtaps = scl_data->taps.v_taps;
487 	int vtaps_c = scl_data->taps.v_taps_c;
573 		SCL_V_NUM_TAPS, scl_data->taps.v_taps - 1,
574 		SCL_H_NUM_TAPS, scl_data->taps.h_taps - 1,
575 		SCL_V_NUM_TAPS_C, scl_data->taps.v_taps_c - 1,
576 		SCL_H_NUM_TAPS_C, scl_data->taps.h_taps_c - 1);
733 		SCL_V_NUM_TAPS, scl_data->taps.v_taps - 1,
734 		SCL_H_NUM_TAPS, scl_data->taps.h_taps - 1,
735 		SCL_V_NUM_TAPS_C, scl_data->taps.v_taps_c - 1,
736 		SCL_H_NUM_TAPS_C, scl_data->taps.h_taps_c - 1);