Lines Matching refs:psr_context
2469 struct psr_context *psr_context)
2478 psr_context->controllerId = CONTROLLER_ID_UNDEFINED;
2519 psr_context->channel = link->ddc->ddc_pin->hw_info.ddc_channel;
2520 psr_context->transmitterId = link->link_enc->transmitter;
2521 psr_context->engineId = link->link_enc->preferred_engine;
2529 psr_context->controllerId =
2537 psr_context->phyType = PHY_TYPE_UNIPHY;
2539 psr_context->smuPhyId =
2542 psr_context->crtcTimingVerticalTotal = stream->timing.v_total;
2543 psr_context->vsync_rate_hz = div64_u64(div64_u64((stream->
2548 psr_context->psrSupportedDisplayConfig = true;
2549 psr_context->psrExitLinkTrainingRequired =
2551 psr_context->sdpTransmitLineNumDeadline =
2553 psr_context->psrFrameCaptureIndicationReq =
2556 psr_context->skipPsrWaitForPllLock = 0; /* only = 1 in KV */
2558 psr_context->numberOfControllers =
2561 psr_context->rfb_update_auto_en = true;
2564 psr_context->timehyst_frames = 2;
2568 psr_context->hyst_lines = stream->timing.v_total / 2 / 100;
2569 psr_context->aux_repeats = 10;
2571 psr_context->psr_level.u32all = 0;
2576 psr_context->psr_level.bits.SKIP_CRTC_DISABLE = true;
2584 psr_context->allow_smu_optimizations = psr_config->allow_smu_optimizations;
2589 psr_context->psr_level.bits.DISABLE_PSR_ENTRY_ABORT = 1;
2594 psr_context->frame_delay = 0;
2597 link->psr_feature_enabled = psr->funcs->setup_psr(psr, link, psr_context);
2599 link->psr_feature_enabled = dmcu->funcs->setup_psr(dmcu, link, psr_context);