Lines Matching refs:adev
57 static void vcn_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev);
58 static void vcn_v2_0_set_enc_ring_funcs(struct amdgpu_device *adev);
59 static void vcn_v2_0_set_irq_funcs(struct amdgpu_device *adev);
62 static int vcn_v2_0_pause_dpg_mode(struct amdgpu_device *adev,
74 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
76 adev->vcn.num_vcn_inst = 1;
77 adev->vcn.num_enc_rings = 2;
79 vcn_v2_0_set_dec_ring_funcs(adev);
80 vcn_v2_0_set_enc_ring_funcs(adev);
81 vcn_v2_0_set_irq_funcs(adev);
97 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
100 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
102 &adev->vcn.inst->irq);
107 for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
108 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
110 &adev->vcn.inst->irq);
115 r = amdgpu_vcn_sw_init(adev);
119 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
121 hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
122 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].ucode_id = AMDGPU_UCODE_ID_VCN;
123 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw;
124 adev->firmware.fw_size +=
129 r = amdgpu_vcn_resume(adev);
133 ring = &adev->vcn.inst->ring_dec;
136 ring->doorbell_index = adev->doorbell_index.vcn.vcn_ring0_1 << 1;
139 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0);
143 adev->vcn.internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET;
144 adev->vcn.internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET;
145 adev->vcn.internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET;
146 adev->vcn.internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET;
147 adev->vcn.internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET;
148 adev->vcn.internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET;
150 adev->vcn.internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET;
151 adev->vcn.inst->external.scratch9 = SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9);
152 adev->vcn.internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET;
153 adev->vcn.inst->external.data0 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0);
154 adev->vcn.internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET;
155 adev->vcn.inst->external.data1 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1);
156 adev->vcn.internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET;
157 adev->vcn.inst->external.cmd = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD);
158 adev->vcn.internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET;
159 adev->vcn.inst->external.nop = SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP);
161 for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
162 ring = &adev->vcn.inst->ring_enc[i];
164 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + i;
166 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0);
171 adev->vcn.pause_dpg_mode = vcn_v2_0_pause_dpg_mode;
186 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
188 r = amdgpu_vcn_suspend(adev);
192 r = amdgpu_vcn_sw_fini(adev);
206 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
207 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
210 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
217 for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
218 ring = &adev->vcn.inst->ring_enc[i];
227 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode");
241 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
242 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
245 if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
246 (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
248 vcn_v2_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
252 for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
253 ring = &adev->vcn.inst->ring_enc[i];
270 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
272 r = vcn_v2_0_hw_fini(adev);
276 r = amdgpu_vcn_suspend(adev);
291 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
293 r = amdgpu_vcn_resume(adev);
297 r = vcn_v2_0_hw_init(adev);
305 * @adev: amdgpu_device pointer
309 static void vcn_v2_0_mc_resume(struct amdgpu_device *adev)
311 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
315 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
317 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo));
319 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi));
324 lower_32_bits(adev->vcn.inst->gpu_addr));
326 upper_32_bits(adev->vcn.inst->gpu_addr));
336 lower_32_bits(adev->vcn.inst->gpu_addr + offset));
338 upper_32_bits(adev->vcn.inst->gpu_addr + offset));
344 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
346 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
350 WREG32_SOC15(UVD, 0, mmUVD_GFX10_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
353 static void vcn_v2_0_mc_resume_dpg_mode(struct amdgpu_device *adev, bool indirect)
355 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
359 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
363 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo), 0, indirect);
366 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi), 0, indirect);
381 lower_32_bits(adev->vcn.inst->gpu_addr), 0, indirect);
384 upper_32_bits(adev->vcn.inst->gpu_addr), 0, indirect);
402 lower_32_bits(adev->vcn.inst->gpu_addr + offset), 0, indirect);
405 upper_32_bits(adev->vcn.inst->gpu_addr + offset), 0, indirect);
422 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
425 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
443 UVD, 0, mmUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect);
449 * @adev: amdgpu_device pointer
454 static void vcn_v2_0_disable_clock_gating(struct amdgpu_device *adev)
460 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
556 static void vcn_v2_0_clock_gating_dpg_mode(struct amdgpu_device *adev,
562 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
607 * @adev: amdgpu_device pointer
612 static void vcn_v2_0_enable_clock_gating(struct amdgpu_device *adev)
618 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
663 static void vcn_v2_0_disable_static_power_gating(struct amdgpu_device *adev)
668 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
703 if (adev->pg_flags & AMD_PG_SUPPORT_VCN)
710 static void vcn_v2_0_enable_static_power_gating(struct amdgpu_device *adev)
715 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
750 static int vcn_v2_0_start_dpg_mode(struct amdgpu_device *adev, bool indirect)
752 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
755 vcn_v2_0_enable_static_power_gating(adev);
764 adev->vcn.inst->dpg_sram_curr_addr = (uint32_t*)adev->vcn.inst->dpg_sram_cpu_addr;
767 vcn_v2_0_clock_gating_dpg_mode(adev, 0, indirect);
816 vcn_v2_0_mc_resume_dpg_mode(adev, indirect);
838 psp_update_vcn_sram(adev, 0, adev->vcn.inst->dpg_sram_gpu_addr,
839 (uint32_t)((uintptr_t)adev->vcn.inst->dpg_sram_curr_addr -
840 (uintptr_t)adev->vcn.inst->dpg_sram_cpu_addr));
876 static int vcn_v2_0_start(struct amdgpu_device *adev)
878 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
883 if (adev->pm.dpm_enabled)
884 amdgpu_dpm_enable_uvd(adev, true);
886 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
887 return vcn_v2_0_start_dpg_mode(adev, adev->vcn.indirect_sram);
889 vcn_v2_0_disable_static_power_gating(adev);
896 vcn_v2_0_disable_clock_gating(adev);
940 vcn_v2_0_mc_resume(adev);
1025 ring = &adev->vcn.inst->ring_enc[0];
1032 ring = &adev->vcn.inst->ring_enc[1];
1042 static int vcn_v2_0_stop_dpg_mode(struct amdgpu_device *adev)
1071 static int vcn_v2_0_stop(struct amdgpu_device *adev)
1076 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
1077 r = vcn_v2_0_stop_dpg_mode(adev);
1129 vcn_v2_0_enable_clock_gating(adev);
1130 vcn_v2_0_enable_static_power_gating(adev);
1133 if (adev->pm.dpm_enabled)
1134 amdgpu_dpm_enable_uvd(adev, false);
1139 static int vcn_v2_0_pause_dpg_mode(struct amdgpu_device *adev,
1147 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) {
1149 adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based);
1169 ring = &adev->vcn.inst->ring_enc[0];
1176 ring = &adev->vcn.inst->ring_enc[1];
1195 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based;
1203 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1210 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1222 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1229 vcn_v2_0_enable_clock_gating(adev);
1232 vcn_v2_0_disable_clock_gating(adev);
1246 struct amdgpu_device *adev = ring->adev;
1260 struct amdgpu_device *adev = ring->adev;
1263 return adev->wb.wb[ring->wptr_offs];
1277 struct amdgpu_device *adev = ring->adev;
1279 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
1284 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
1300 struct amdgpu_device *adev = ring->adev;
1302 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0));
1304 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
1317 struct amdgpu_device *adev = ring->adev;
1319 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
1332 struct amdgpu_device *adev = ring->adev;
1338 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.nop, 0));
1354 struct amdgpu_device *adev = ring->adev;
1357 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.context_id, 0));
1360 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0));
1363 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0));
1366 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
1369 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0));
1372 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0));
1375 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
1393 struct amdgpu_device *adev = ring->adev;
1396 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.ib_vmid, 0));
1399 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.ib_bar_low, 0));
1401 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.ib_bar_high, 0));
1403 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.ib_size, 0));
1410 struct amdgpu_device *adev = ring->adev;
1412 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0));
1415 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0));
1418 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.gp_scratch8, 0));
1421 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
1429 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
1444 struct amdgpu_device *adev = ring->adev;
1446 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0));
1449 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0));
1452 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
1466 struct amdgpu_device *adev = ring->adev;
1468 if (ring == &adev->vcn.inst->ring_enc[0])
1483 struct amdgpu_device *adev = ring->adev;
1485 if (ring == &adev->vcn.inst->ring_enc[0]) {
1487 return adev->wb.wb[ring->wptr_offs];
1492 return adev->wb.wb[ring->wptr_offs];
1507 struct amdgpu_device *adev = ring->adev;
1509 if (ring == &adev->vcn.inst->ring_enc[0]) {
1511 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
1518 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
1585 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
1601 static int vcn_v2_0_set_interrupt_state(struct amdgpu_device *adev,
1609 static int vcn_v2_0_process_interrupt(struct amdgpu_device *adev,
1617 amdgpu_fence_process(&adev->vcn.inst->ring_dec);
1620 amdgpu_fence_process(&adev->vcn.inst->ring_enc[0]);
1623 amdgpu_fence_process(&adev->vcn.inst->ring_enc[1]);
1636 struct amdgpu_device *adev = ring->adev;
1641 WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD);
1645 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
1647 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.scratch9, 0));
1650 for (i = 0; i < adev->usec_timeout; i++) {
1651 tmp = RREG32(adev->vcn.inst[ring->me].external.scratch9);
1657 if (i >= adev->usec_timeout)
1675 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1677 if (state == adev->vcn.cur_state)
1681 ret = vcn_v2_0_stop(adev);
1683 ret = vcn_v2_0_start(adev);
1686 adev->vcn.cur_state = state;
1770 static void vcn_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev)
1772 adev->vcn.inst->ring_dec.funcs = &vcn_v2_0_dec_ring_vm_funcs;
1776 static void vcn_v2_0_set_enc_ring_funcs(struct amdgpu_device *adev)
1780 for (i = 0; i < adev->vcn.num_enc_rings; ++i)
1781 adev->vcn.inst->ring_enc[i].funcs = &vcn_v2_0_enc_ring_vm_funcs;
1791 static void vcn_v2_0_set_irq_funcs(struct amdgpu_device *adev)
1793 adev->vcn.inst->irq.num_types = adev->vcn.num_enc_rings + 1;
1794 adev->vcn.inst->irq.funcs = &vcn_v2_0_irq_funcs;