Lines Matching defs:reg_data
559 uint32_t reg_data = 0;
563 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
565 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
566 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
567 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
568 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
589 UVD, 0, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect);
1143 uint32_t reg_data = 0;
1150 reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) &
1160 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
1161 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);
1192 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
1193 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);