amd/amdgpu/amdgpu_uvd.c

91  * amdgpu_uvd_cs_ctx - Command submission parser context
96 	struct amdgpu_cs_parser *parser;
479 	lo = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data0);
480 	hi = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data1);
489  * @ctx: UVD parser context
503 	r = amdgpu_cs_find_mapping(ctx->parser, addr, &bo, &mapping);
509 	if (!ctx->parser->adev->uvd.address_64_bit) {
511 		cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx) >> 1;
722  * @ctx: UVD parser context
732 	struct amdgpu_device *adev = ctx->parser->adev;
773 				adev->uvd.filp[i] = ctx->parser->filp;
791 				if (adev->uvd.filp[i] != ctx->parser->filp) {
820  * @ctx: UVD parser context
833 	r = amdgpu_cs_find_mapping(ctx->parser, addr, &bo, &mapping);
847 	amdgpu_set_ib_value(ctx->parser, ctx->ib_idx, ctx->data0,
849 	amdgpu_set_ib_value(ctx->parser, ctx->ib_idx, ctx->data1,
852 	cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx) >> 1;
873 	if (!ctx->parser->adev->uvd.address_64_bit) {
881 		    (start >> 28) != (ctx->parser->adev->uvd.inst->gpu_addr >> 28)) {
904  * @ctx: UVD parser context
912 	struct amdgpu_ib *ib = &ctx->parser->job->ibs[ctx->ib_idx];
951  * @ctx: UVD parser context
959 	struct amdgpu_ib *ib = &ctx->parser->job->ibs[ctx->ib_idx];
963 		uint32_t cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx);
985  * amdgpu_uvd_ring_parse_cs - UVD command submission parser
987  * @parser: Command submission parser context
991 int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser, uint32_t ib_idx)
1001 	struct amdgpu_ib *ib = &parser->job->ibs[ib_idx];
1004 	parser->job->vm = NULL;
1013 	ctx.parser = parser;
1018 	if (!parser->adev->uvd.address_64_bit) {