amd/amdgpu/amdgpu_soc15.c

208 	address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
209 	data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
222 	address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
223 	data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
237 	WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
238 	r = RREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA);
248 	WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
249 	WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, (v));
259 	WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
260 	r = RREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA);
270 	WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
271 	WREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA, (v));
300 	WREG32_SOC15_RLC_SHADOW(GC, 0, mmGRBM_GFX_CNTL, grbm_gfx_cntl);
341 	{ SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},
342 	{ SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
343 	{ SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)},
344 	{ SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)},
345 	{ SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)},
346 	{ SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)},
349 	{ SOC15_REG_ENTRY(GC, 0, mmCP_STAT)},
350 	{ SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)},
351 	{ SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)},
352 	{ SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)},
353 	{ SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)},
354 	{ SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)},
355 	{ SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)},
356 	{ SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)},
357 	{ SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)},
358 	{ SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
359 	{ SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)},
360 	{ SOC15_REG_ENTRY(GC, 0, mmDB_DEBUG2)},
387 		if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
389 		else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2))
448 		if (reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3) ||
449 			reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE) ||
450 			reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1) ||
451 			reg == SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG))