amd/amdgpu/amdgpu_sdma_v4_0.c

83 #define WREG32_SDMA(instance, offset, value) \
721 		WREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR,
723 		WREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI,
772 		WREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR,
774 		WREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR_HI,
929 		WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl);
932 		WREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL, ib_cntl);
976 		WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl);
980 		WREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL, ib_cntl);
1028 			WREG32_SDMA(i, mmSDMA0_PHASE0_QUANTUM, phase_quantum);
1029 			WREG32_SDMA(i, mmSDMA0_PHASE1_QUANTUM, phase_quantum);
1030 			WREG32_SDMA(i, mmSDMA0_PHASE2_QUANTUM, phase_quantum);
1032 		WREG32_SDMA(i, mmSDMA0_CNTL, f32_cntl);
1060 		WREG32_SDMA(i, mmSDMA0_F32_CNTL, f32_cntl);
1103 	WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl);
1106 	WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR, 0);
1107 	WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_HI, 0);
1108 	WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR, 0);
1109 	WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_HI, 0);
1112 	WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_ADDR_HI,
1114 	WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_ADDR_LO,
1120 	WREG32_SDMA(i, mmSDMA0_GFX_RB_BASE, ring->gpu_addr >> 8);
1121 	WREG32_SDMA(i, mmSDMA0_GFX_RB_BASE_HI, ring->gpu_addr >> 40);
1126 	WREG32_SDMA(i, mmSDMA0_GFX_MINOR_PTR_UPDATE, 1);
1136 	WREG32_SDMA(i, mmSDMA0_GFX_DOORBELL, doorbell);
1137 	WREG32_SDMA(i, mmSDMA0_GFX_DOORBELL_OFFSET, doorbell_offset);
1142 	WREG32_SDMA(i, mmSDMA0_GFX_MINOR_PTR_UPDATE, 0);
1146 	WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO,
1148 	WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI,
1154 	WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, wptr_poll_cntl);
1158 	WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl);
1166 	WREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL, ib_cntl);
1193 	WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl);
1196 	WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR, 0);
1197 	WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_HI, 0);
1198 	WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR, 0);
1199 	WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_HI, 0);
1202 	WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_ADDR_HI,
1204 	WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_ADDR_LO,
1210 	WREG32_SDMA(i, mmSDMA0_PAGE_RB_BASE, ring->gpu_addr >> 8);
1211 	WREG32_SDMA(i, mmSDMA0_PAGE_RB_BASE_HI, ring->gpu_addr >> 40);
1216 	WREG32_SDMA(i, mmSDMA0_PAGE_MINOR_PTR_UPDATE, 1);
1226 	WREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL, doorbell);
1227 	WREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL_OFFSET, doorbell_offset);
1233 	WREG32_SDMA(i, mmSDMA0_PAGE_MINOR_PTR_UPDATE, 0);
1237 	WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO,
1239 	WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI,
1245 	WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, wptr_poll_cntl);
1249 	WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl);
1257 	WREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL, ib_cntl);
1371 		WREG32_SDMA(i, mmSDMA0_UCODE_ADDR, 0);
1374 			WREG32_SDMA(i, mmSDMA0_UCODE_DATA,
1377 		WREG32_SDMA(i, mmSDMA0_UCODE_ADDR,
1418 		WREG32_SDMA(i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL, 0);
1426 		WREG32_SDMA(i, mmSDMA0_CNTL, temp);
1432 			WREG32_SDMA(i, mmSDMA0_F32_CNTL, temp);
2015 	WREG32_SDMA(type, mmSDMA0_CNTL, sdma_cntl);
2100 	WREG32_SDMA(type, mmSDMA0_EDC_CONFIG, sdma_edc_config);
2124 				WREG32_SDMA(i, mmSDMA0_CLK_CTRL, data);
2138 				WREG32_SDMA(i, mmSDMA0_CLK_CTRL, data);
2157 				WREG32_SDMA(0, mmSDMA0_POWER_CNTL, data);
2165 				WREG32_SDMA(0, mmSDMA0_POWER_CNTL, data);