amd/amdgpu/amdgpu_nbio_v7_0.c

41 static void nbio_v7_0_remap_hdp_registers(struct amdgpu_device *adev)
44 		adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);
46 		adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);
49 static u32 nbio_v7_0_get_rev_id(struct amdgpu_device *adev)
59 static void nbio_v7_0_mc_access_enable(struct amdgpu_device *adev, bool enable)
68 static void nbio_v7_0_hdp_flush(struct amdgpu_device *adev,
72 		WREG32_NO_KIQ((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
74 		amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
77 static u32 nbio_v7_0_get_memsize(struct amdgpu_device *adev)
82 static void nbio_v7_0_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
99 static void nbio_v7_0_vcn_doorbell_range(struct amdgpu_device *adev, bool use_doorbell,
119 static void nbio_v7_0_enable_doorbell_aperture(struct amdgpu_device *adev,
125 static void nbio_v7_0_enable_doorbell_selfring_aperture(struct amdgpu_device *adev,
131 static void nbio_v7_0_ih_doorbell_range(struct amdgpu_device *adev,
145 static uint32_t nbio_7_0_read_syshub_ind_mmr(struct amdgpu_device *adev, uint32_t offset)
155 static void nbio_7_0_write_syshub_ind_mmr(struct amdgpu_device *adev, uint32_t offset,
162 static void nbio_v7_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
170 	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG))
179 	def = data = nbio_7_0_read_syshub_ind_mmr(adev, ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK);
181 	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG))
187 		nbio_7_0_write_syshub_ind_mmr(adev, ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK, data);
190 	def = data = nbio_7_0_read_syshub_ind_mmr(adev, ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK);
192 	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG))
198 		nbio_7_0_write_syshub_ind_mmr(adev, ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK, data);
201 static void nbio_v7_0_update_medium_grain_light_sleep(struct amdgpu_device *adev,
207 	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) {
221 static void nbio_v7_0_get_clockgating_state(struct amdgpu_device *adev,
237 static void nbio_v7_0_ih_control(struct amdgpu_device *adev)
242 	WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8);
253 static u32 nbio_v7_0_get_hdp_flush_req_offset(struct amdgpu_device *adev)
258 static u32 nbio_v7_0_get_hdp_flush_done_offset(struct amdgpu_device *adev)
263 static u32 nbio_v7_0_get_pcie_index_offset(struct amdgpu_device *adev)
268 static u32 nbio_v7_0_get_pcie_data_offset(struct amdgpu_device *adev)
288 static void nbio_v7_0_detect_hw_virt(struct amdgpu_device *adev)
291 		adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE;
294 static void nbio_v7_0_init_registers(struct amdgpu_device *adev)